KeywordsInitial Code Verification Software Code Coverage Faulty Behavior Clock Domain
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- Bergeron J (2003) Writing Testbenches: Functional Verification of HDL Models, Second Edition. Kluwer Academic Publishers.Google Scholar
- Bergeron J, Cerny E, Hunter A, Nightingale A (2005) Verification Methodology Manual for SystemVerilog. Springer.Google Scholar
- Foster HD, Krolnik A, and Lacey D (2004) Assertion-Based Design, 2nd Edition.Google Scholar
- Francard R, Posner M (2006) Verification Methods Applied to the ST Microelectronics GreenSIDE Project. Design And Reuse.Google Scholar
- Haque FI, Khan KA, Michelson J (2001) The Art of Verification with Vera. Verification Central.Google Scholar
- Palnitkar S (2004) Design Verification with e. Prentice Hall Professional Technical Reference.Google Scholar
- Synopsys (2003) Constrained-Random Test Generation and Functional Coverage with Vera.Google Scholar
- Talesara H, Mullinger N (2006) Accelerating Functional Closure: Synopsys Verification Solutions. Synopsys, Inc.Google Scholar
- Wile B, Goss JC, Roesner W (2005) Comprehensive Functional Verification. Elsevier/Morgan Kaufman.Google Scholar
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