Abstract
Time in Verilog is a 64-bit unsigned integer. Delays are specified by using a hash mark (#) followed by a number. A delay does not have any indication of what unit of time is being represented.
Note: the code examples in this chapter are contrived in order to illustrate each gotcha using small examples. In real design and verification code, these gotchas might not be as obvious or easy to debug.
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References
SystemVerilog 3.1a Language Reference Manual: Accellera’s Extensions to Verilog, Copyright 2004 by Accellera Organization, Inc., Napa, CA, http://www.eda.org/sv/SystemVerilog_3.1a.pdf.
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© 2007 Springer Science+Business Media, LLC
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Sutherland, S., Mills, D. (2007). Tool Compatibility Gotchas. In: Verilog and SystemVerilog Gotchas. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-71715-9_8
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DOI: https://doi.org/10.1007/978-0-387-71715-9_8
Publisher Name: Springer, Boston, MA
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