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Declaration and Literal Number Gotchas

  • Stuart Sutherland
  • Don Mills
Chapter

Abstract

An identifier in Verilog and SystemVerilog is the user-specified name of some object, such as the name of a module, wire, variable, or function. Verilog and System Verilog are case-sensitive languages, meaning that lowercase letters and uppercase letters are perceived as different in identifiers and in keywords. Keywords are always in all lowercase letters. User-created identifiers can use a mix of lowercase and uppercase letters, as well as numbers and the special characters _, $, and \ (the latter is an escape character).

Keywords

Sign Extension Size Mismatch Input Logic Input Wire Automatic Storage 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Stuart Sutherland
    • 1
  • Don Mills
    • 2
  1. 1.Sutherland HDL, Inc.TualatinUSA
  2. 2.LCDM EngineeringChandlerUSA

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