Delay Insertion and Clock Skew Scheduling

As briefly mentioned in Chapter 4, delay insertion into the logic network1 can be used as a post-processing step in mainstream digital integrated circuit design flow in order to solve the short-path (hold time) timing violations of synchronous circuits. The drawbacks of delay insertion, such as increased circuit area and power dissipation, are usually disregarded in favor of achieving a feasible timing schedule.

In this chapter, a delay insertion algorithm into the logic network that improves the efficiency and results of clock skew scheduling is presented. By systematic delay insertion, a higher operating speed or improved reliability is achieved through clock skew scheduling. It is known that the minimum clock period of a synchronous circuit achievable through clock skew scheduling is limited by the uncertainties of the data propagation times on local data paths [2] and the total data propagation times on data path loops [117]2. It has been shown recently by Taskin [132] that the reconvergent local data paths also introduce an additional theoretical limit on the minimum clock period of a synchronous circuit achievable through clock skew scheduling. This limitation caused by reconvergent paths is theoretically derived and a delay insertion method is defined in order to mitigate this limitation. Overall, these limitations can be used to quickly and efficiently calculate the improvements achievable through clock skew scheduling, without having to apply clock skew scheduling. Based on the improvements achievable for a particular circuit, the design team can decide whether or not to allocate resources in the design budget to perform clock skew scheduling and non-zero clock skew clock tree synthesis.


Clock Cycle Delay Interval Data Path Path Delay Delay Element 
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© Springer Science+Business Media, LLC 2009

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