Clock Skew Scheduling for Improved Reliability

The operation of a fully synchronous digital system has been discussed in detail in Chapters 1 through 5. Briefly, in order for such systems to function properly, a strict temporal ordering of the many thousands of switching events within the circuit is required. This strict ordering is enforced by a global synchronizing clock signal delivered to every register in a circuit by a clock distribution network. Algorithms for determining a non-zero clock skew schedule that satisfy the tighter timing constraints of high speed, VLSI complexity systems have been presented in detail in Chapter 5.

In this chapter, the problem of determining an optimal clock skew schedule for a fully synchronous VLSI system is considered in this chapter from the perspective of improving system reliability. An original formulation of the clock skew scheduling problem by Kourtev and Friedman is introduced as a constrained quadratic programming (QP) problem [121, 122]. In this formulation, the primary objective is to improve circuit reliability by maximizing the tolerance to process parameter variations. As the initial step of the computation process, first an objective is computed for the clock skew value of each local data path. Then, a consistent clock schedule is found by applying the proposed optimization algorithm. Unlike the approach discussed in Chapter 5, the algorithm presented in this chapter minimizes the least square error between the computed and objective clock skew schedules.1 It should also be mentioned that a secondary objective of the clock skew scheduling algorithm presented in this chapter is to increase the system-wide clock frequency.


Span Tree Quadratic Programming Clock Period Improve Reliability Permissible Range 
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© Springer Science+Business Media, LLC 2009

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