Clock Skew Scheduling of Level-Sensitive Circuits

Level-sensitive circuits are gaining popularity in the state-of-the-art high-performance synchronous circuit design due to their smaller size, lower power consumption and faster operation speeds [109, 110, 111]. The timing analysis of level-sensitive circuits, however, is more difficult due to the non-linearity of the timing constraints caused by the transparent latch operation discussed in Section 4.2. Traditionally, the non-linearity of constraints has been resolved with one of two approaches. On one hand, analyses which aim to accurately model the effects of time borrowing have been considered too optimistic and this property is fully disregarded from the analysis [69, 72]. More recently, the non-linear constraints of operation are relaxed using iterative solution techniques [73, 94, 99, 100]. The iterative solution techniques are practical for timing analysis where clock skew values (zero or non-zero) are known. However, these techniques are not applicable in clock skew scheduling computation. In this chapter, a linear programming (LP) formulation applicable to the timing analysis of large-scale level-sensitive synchronous circuits is presented. The presented LP formulation accurately models the effects of time borrowing. This LP formulation is computationally efficient due to the linearization of non-linear constraints, and the formulation and solution processes are fully-automated.


Clock Cycle Linear Programming Model Data Path Clock Signal Clock Period 
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© Springer Science+Business Media, LLC 2009

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