Clock Skew Scheduling and Clock Tree Synthesis

The basic principles of operation of a synchronous digital VLSI system are described in Chapter 2. As demonstrated in Chapter 3, the propagation of signals through logic gates and interconnections requires a certain amount of time to complete. Therefore, a timing discipline is necessary to ensure that logical computations whether executing concurrently or in sequence—operate on the proper data signals. As described in Chapter 4, this timing discipline is implemented by inserting storage elements, or registers, throughout the circuit. Also analyzed in Chapter 4 are the timing relationships among signals in local data paths based on the type of clock signal and storage element. Recall from Chapter 4 the relationships that must be satisfied in order for a local data path to operate properly [inequalities (4.8), (4.13), (4.23), (4.24), (4.29), (4.39), (4.40) and (4.45)]. These relationships are written in the form of bounds on the clock skew T Skew in order to emphasize that bounds are imposed on T Skew by various parameters of the data paths and the clock signal. If any of the inequalities (4.8), (4.13), (4.23), (4.24), (4.29), (4.39), (4.40) and (4.45) is not satisfied, a timing violation occurs.

A methodology and software system for determining (or scheduling) the values of the clock skew T Skew based on the timing constraints of a fully synchronous digital VLSI system and for synthesizing the clock distribution network so as to implement these target clock skew values is described in this chapter. The relation of synchronization to the design of the clock distribution network is presented in Section 5.1. Some useful definitions and notations are introduced in Section 5.2. The clock skew scheduling problem for more popular register type of edge-triggered flip-flops is described in Section 5.3. Various formulations of timing problem with the presented timing constraints are briefed in Section 5.4. The structure of the clock distribution network is examined from the perspective of clock skew scheduling in Section 5.5. The proposed algorithms are described in Section 5.6. Finally, the software programs developed to implement the algorithm and the demonstration of these programs on benchmark and industrial circuits are described in Section 5.7.


Logic Gate Clock Signal Path Delay Clock Period Benchmark Circuit 
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© Springer Science+Business Media, LLC 2009

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