Timing Properties of Synchronous Systems
The general structure and principles for operating a fully synchronous digital VLSI system are described in Chapter 2. The combinational logic and the storage elements make up the computational circuitry used to implement a specific synchronous system. The clock distribution network provides the time reference for the storage elements—or registers—thereby enforcing the required logical order of operations. This time reference consists of one or more clock signals that are delivered to each and every register within the integrated circuit. These clock signals control the order of computational events by controlling the exact times the register data input signals are sampled.
As shown in Chapter 3, the data signals are inevitably delayed as these signals propagate through the logic gates and along interconnections within the local data paths. These propagation delays can be evaluated within a certain accuracy and used to derive timing relationships among the signals within a circuit. In this chapter, the properties of commonly used types of registers and their local timing relationships for different types of local data paths are described. After discussing registers in general in Section 4.1, the properties of level-sensitive registers (latches) and the significant timing parameters characterizing these registers are reviewed in Sections 4.2 and 4.3, respectively. Edge-sensitive registers (flip-flops) and the timing parameters are analyzed in Sections 4.4 and 4.5, respectively. Properties and definitions related to the clock distribution network are reviewed in Section 4.6. The mathematical foundation for analyzing timing violations in flip-flops and latches for single-phase operation, and latches for multi-phase operation are discussed in Sections 4.7, 4.8 and 4.9, respectively, followed by some final comments in Section 4.10.
KeywordsClock Cycle Data Signal Clock Signal Early Arrival Combinational Logic
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