Signal Delay in VLSI Systems
In order to understand the timing characteristics of a synchronous digital system—specifically, the delays within the data paths and clock distribution network—a more complete understanding of the properties of signal delay in VLSI systems is necessary. The topic of signal delay in VLSI-based systems is examined in detail in this chapter. Delay metrics are first analyzed and certain definitions are introduced in Section 3.1. A more thorough analytical treatment of the subject of computing delay in CMOS integrated circuits is presented in Section 3.2.
KeywordsPropagation Delay Logic Gate Signal Delay Current Gain Capacitive Load
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