The results of the various clock skew scheduling methodologies described in this research monograph are presented in this chapter. Results of each application are presented in dedicated sections for a thorough analysis and simplicity in presentation. For comparison of results, identical experimental setups are used where possible and publicly available ISCAS'89 benchmark circuits are used as test subjects. Presented results entail explanations of experimental setups for replicability, detailed reports (presented in tabular form) of experiment runs including circuit statistics, reported improvements and runtimes, and interpretation of results for observed trends or deviations from norms.
Specifically, experimental results for the following methodologies are presented: In Section 11.1, the results for the clock skew scheduling of level-sensitive circuit results are shown. These results also include edge-triggered circuit implementation results (presented earlier in Chapter 5) for side-by-side comparison. In Section 11.2, the level-sensitive circuit results that are expanded for multi-phase clock synchronization are shown. The effects of multi-phase clocking are interpreted for best synchronization practices, which is particularly useful for rotary clock synchronized circuits. In Section 11.3, the performance of quadratic programming (QP) formulation proposed for maximizing safety against variations is shown. In Section 11.4, the improvement of clock skew scheduling results for edge-triggered and level-sensitive circuits by applying the delay insertion method is shown. In Section 11.5, preliminary results for the proof-of-concept physical design methodology for rotary-clock-synchronized circuits are shown.
KeywordsData Path Clock Period Benchmark Circuit Permissible Range Clock Phase
Unable to display preview. Download preview PDF.