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Part of the book series: Series on Integrated Circuits and Systems ((ICIR))

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Although BMC can find bugs in larger designs than BDD-based methods, the correctness of a property is guaranteed only for the analysis bound. However, one can augment BMC for performing proofs by induction [66, 67]. A completeness bound has been proposed [66, 67], to provide an inductive proof of correctness for safety properties based on the longest loop-free path between states.

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(2007). Proof by Induction. In: SAT-Based Scalable Formal Verification Solutions. Series on Integrated Circuits and Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-69167-1_9

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  • DOI: https://doi.org/10.1007/978-0-387-69167-1_9

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-0-387-69166-4

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