Synthesis for Verification
To overcome increasing demand for shorter time-to-market and complex designs, significant efforts are being made in high-level synthesis methodologies, design languages and verification methodologies to leverage the expressive power of high-level models and reduce the design cycle time. However, with progression through each stage in the design cycle from abstraction to realization, part of the high-level information gets lost; which can adversely affect the performance and optimality of the verification solution at that stage.
KeywordsFlow Graph Control Flow Graph Bound Model Check Entry Node Loop Period
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