Synthesis for Verification

Part of the Series on Integrated Circuits and Systems book series (ICIR)

To overcome increasing demand for shorter time-to-market and complex designs, significant efforts are being made in high-level synthesis methodologies, design languages and verification methodologies to leverage the expressive power of high-level models and reduce the design cycle time. However, with progression through each stage in the design cycle from abstraction to realization, part of the high-level information gets lost; which can adversely affect the performance and optimality of the verification solution at that stage.


Flow Graph Control Flow Graph Bound Model Check Entry Node Loop Period 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer Science+Business Media, LLC 2007

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