Design Verification Challenges

Part of the Series on Integrated Circuits and Systems book series (ICIR)

Verification ensures that the design meets the specification and has become an indispensable part of a product development cycle of a digital hardware design. Cost of chip failure is enormous due to high cost of respins and delayed tape-out, resulting in loss of opportunity to launch product on time in a highly competitive market. With the increasing design complexity of digital hardware, functional verification has become increasingly on the critical path of the cycle [1], requiring expensive and time-consuming efforts, as much as 70% of the product development cycle. As per the 2002/2004 functional verification study conducted by Collett International Research (as reported by [2]), functional/logic flaws account for 75% causes for respins of more than two-thirds of IC/ASIC designs to reach volume. Of these 75% flaws, more than 80% are due to design errors and remaining are due to incorrect/incomplete specification, internal and external IPs. Market forces mandate scalable verification solutions and radical shifts in design methodology to overcome the difficulty in verifying complex designs. Not surprisingly, traditional “black-box” verification methodology is giving way to “white-box” verification methodology, where more than half of the engineers in the design team are verification engineers who are getting involved in the early phase of design and specification.


Model Check Formal Verification Verification Task Register Transfer Level Verification Technique 
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Copyright information

© Springer Science+Business Media, LLC 2007

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