Ensuring Interconnect Planarity

Variations in the back end are often related to pattern dependencies, as discussed in Chapter 3. These include both feature level variations, due to process interactions with features of different sizes, and regional or chip scale variations, often due to pattern density differences at various locations within the chip. An important approach to reduce the occurrence or severity of pattern dependencies is to modify the layout to be more “regular” – that is, to have a more limited range in pattern density or a restricted set of feature sizes. In some cases, the circuit design might be able to be modified or generated directly to achieve such improved layout regularity. In many cases, however, post-processing of the layout can be performed to insert “dummy fill” or additional layout geometries, which are non-functional from an electrical perspective, but which serve to improve the layout regularity. Figure 8.1 shows a schematic illustration of three dummy fill options in the case of copper interconnect.

In this chapter, we discuss dummy fill from three perspectives. We begin with an overview of dummy fill strategies and issues for copper interconnect. The goal from a process physics perspective is discussed, together with strategies for understanding the possible negative impact of inserted dummy structures, primarily revolving around additional capacitance that might result. We next review a number of algorithmic challenges and strategies related to dummy fill. Finally, additional dummy fill issues and opportunities for other process steps and layers are discussed, including for copper electroplating and shallow trench isolation.


Pattern Density Pattern Dependency Layout Pattern Shallow Trench Isolation Copper Thickness 
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© Springer Science+Business Media, LLC 2008

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