The previous chapters have been concerned with the modeling and analysis of the impact of process variability on circuit timing, leakage, and parametric yield. We also discussed techniques to compensate for the impact of systematic sources of variation. In this chapter we discuss optimization strategies for minimizing the impact of random variability on parametric yield. Specifically, we explore the emerging methods for full-chip statistical optimization with the purpose of minimizing parametric yield loss. Traditional circuit optimization methods are not sufficient for dealing with large-scale variability because they lack the explicit notion of parameter variance. We discuss the possible formulations of optimization under stochastic variability using robust and chance-constrained optimization formulations. These techniques permit efficient statistical circuit tuning using gate and transistor sizing and the use of multiple threshold voltages.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
Rights and permissions
Copyright information
© 2008 Springer Science+Business Media, LLC
About this chapter
Cite this chapter
(2008). Parametric Yield Optimization. In: Design for Manufacturability and Statistical Design. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-69011-7_12
Download citation
DOI: https://doi.org/10.1007/978-0-387-69011-7_12
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-30928-6
Online ISBN: 978-0-387-69011-7
eBook Packages: EngineeringEngineering (R0)