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Parametric Yield Optimization

The previous chapters have been concerned with the modeling and analysis of the impact of process variability on circuit timing, leakage, and parametric yield. We also discussed techniques to compensate for the impact of systematic sources of variation. In this chapter we discuss optimization strategies for minimizing the impact of random variability on parametric yield. Specifically, we explore the emerging methods for full-chip statistical optimization with the purpose of minimizing parametric yield loss. Traditional circuit optimization methods are not sufficient for dealing with large-scale variability because they lack the explicit notion of parameter variance. We discuss the possible formulations of optimization under stochastic variability using robust and chance-constrained optimization formulations. These techniques permit efficient statistical circuit tuning using gate and transistor sizing and the use of multiple threshold voltages.

Keywords

Parametric Yield Path Delay Timing Yield Deterministic Optimization Leakage Power 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2008

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