Statistical Static Timing Analysis
Information about parameter variability must be propagated to the system level. In this chapter we discuss methods for timing analysis of digital systems using statistical techniques. At system level, timing analysis is concerned with ensuring that all sampled memory elements of a circuit have the proper logical value at the end of each clock cycle. Verifying this property first requires that under no circumstances does the computation of the correct logical value require longer than the clock cycle of a device. Secondly it requires that the latching of the correct logical value be not pre-empted by any rapid propagation of the results of the previous clock cycle.
KeywordsModel Order Reduction Path Delay Acceptance Region Cell Delay Timing Graph
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