The first part of this chapter describes examples of NMOS, CMOS and BiCMOS logic units. The presence of both NMOS and PMOS in an integrated bulk1 CMOS process makes the circuit susceptible to a parasitic effect known as latch-up. A CMOS inverter will be used to describe the latch-up mechanism and methods to prevent it. The second part of the chapter covers different types of memory cells, including dynamic random-access memory, DRAM; static random-access memory, SRAM; and nonvolatile memory, NVM. The chapter concludes with a summary of BiCMOS features that are important for analog/RF applications


Threshold Voltage Gate Oxide Nonvolatile Memory Soft Error Static Random Access Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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