Silicon Devices and Process Integration pp 369-437 | Cite as

# Analog Devices and Passive Components

Analog devices allow the design of circuits whose inputs and outputs are continuously varying quantities, such as resistance, capacitance, current, and voltage. The measured analog signal has an infinite number of possible values. The information is conveyed by the instantaneous value of the signal. Initially, analog circuits were designed primarily with bipolar transistors (Chap. 3). Analog *MOSFET*s, however, have become increasingly important because of their higher packing density, lower cost, high input impedance, and performance that has gradually approached that of bipolar transistors

While several component parameters can be simultaneously optimized for digital and analog applications, there are specific analog requirements that are different from digital. In particular, the trend in high-performance, high-density digital *MOSFET*s is to reduce the size to deep submicron and nanoscale dimensions and operate at supply voltages as low as about 0.8 V, while analog devices typically require higher voltages and hence larger dimensions, particularly to ensure a sufficiently large signal-to-noise ratio. Other parameters, such as high transistor cut-off frequency, high maximum oscillation frequency, and high Early voltage, low bipolar base resistance, low component mismatch, and low noise, are of particular importance to analog applications. The relative importance of these parameters depends on application. When mixed analog and digital components are designed on the same die, such as in system on a chip (SoC), there is a trade-off between simultaneously optimizing the two sets of components and manufacturing cost

## Keywords

Sheet Resistance Drain Current Passive Component Analog Device Dielectric Absorption## Preview

Unable to display preview. Download preview PDF.

## References

- 1.J. E. Lilienfeld, “Method and Apparatus for Controlling Electric Current,” US patent #1,745,175, issued January 28, 1930. Filed: Canadian application October 1925, US application October 1926.Google Scholar
- 2.J. E. Lilienfeld, “Device for Controlling Electric Currents,” US patent 1,900,018, issued March 7, 1933, filed March 1928.Google Scholar
- 3.O. Heil, “Improvements in or Relating to Electrical Amplifiers and other Control Arrangements,” U.K. patent 439, 457, issued December 1935, filed March 1935.Google Scholar
- 4.W. Shockley, “A unipolar ‘field-effect’ transistor,” Proc. IEEE, 40 (11), 1365–1376, 1952.Google Scholar
- 5.J. C. Guo, “Halo and LDD engineering for multiple V
_{TH}high performance analog CMOS devices,” IEEE Trans. Semcon. Manuf., 20 (3), 313–322, 2007.CrossRefGoogle Scholar - 6.E. A. Vittoz, “Future of analog in the VLSI environment,” Proc. ISCASM, 1372–1375, 1990.Google Scholar
- 7.K. Bult, “Analog broadband communication circuits in pure digital deep sub-micron CMOS,” IEEE ISSCC Tech. Dig., 76–78, 1999.Google Scholar
- 8.J. J. P. Bruines, “Process outlook for analog and RF applications,” Microelectron. Eng., 54, 35–48, 2000.CrossRefGoogle Scholar
- 9.N. H. E. West and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley Publishing Company, 1993.Google Scholar
- 10.T. N. Buti, S. Ogura, N. Rovedo, and K. Tobimatsu, “A new asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half-micrometer n-MOSFET design for reliability and performance,” IEEE Trans. Electron Dev., 38 (8), 1757–1764, 1991.CrossRefGoogle Scholar
- 11.H. Shin and L. Lee, “A 0.1-μm asymmetric halo by large-angle-tilt implant (AHLATI) MOS-FET for high performance and reliability,” IEEE Trans. Electron Dev., 46 (4), 820–822, 1999.MathSciNetCrossRefGoogle Scholar
- 12.B. Cheng, V. R. Rao, and J. C. S. Woo, “Exploration of velocity overshoot in a high-performance deep sub-0.1-μm SOI MOSFET with asymmetric channel profile,” IEEE Electron Dev. Lett., 20 (10), 538–540, 1999.CrossRefGoogle Scholar
- 13.D. G. Borse, K. N. M. Rani, N. K. Jha, A. N. Chandorkar, J. Vasi, V. R. Rao, B. Cheng, and J. C. S. Woo, “Optimization and realization of sub-100-nm channel length single halo p-MOSFETs,” IEEE Trans. Electron Dev., 49 (6), 1077–1079, 2002.CrossRefGoogle Scholar
- 14.H. V. Deshpande, B. Cheng, and J. C. S. Woo, “Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications,” IEEE Trans. Electron Dev., 49 (9), 1558–1565, 2002.CrossRefGoogle Scholar
- 15.K. Narasimhulu, D. K. Sharma, and V. R. Rao, “Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance,” IEEE Trans. Electron Dev., 50 (12), 2481–2488, 2003.CrossRefGoogle Scholar
- 16.K. Narasimhulu, M. P. Desai, S. G. Narendra, and V. R. Rao, “The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance,” IEEE Trans. Electron Dev., 51 (9), 1416–1422, 2004.CrossRefGoogle Scholar
- 17.J. H. Song, Y. J. Park, and H. S. Min, “Drain current enhancement due to velocity overshoot effects and its analytical modeling,” IEEE Trans. Electron Dev., 43 (11), 1870–1974, 1996.CrossRefGoogle Scholar
- 18.M. Lundstrom, “Elementary scattering theory of the Si MOSFET,” IEEE Electron Dev. Lett., 18 (7), 361–363, 1997.CrossRefGoogle Scholar
- 19.H. S. Shin, C. Lee, S. W. Wang, B. G. Park, and H. S. Min, “Channel length independent subthreshold characteristics in submicron MOSFETs,” IEEE Electron Dev. Lett., 19 (4), 137–139, 1998.CrossRefGoogle Scholar
- 20.E. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operation,” IEEE J. Solid-State Circuits, SC-12 (3), 224–231, 1977.CrossRefGoogle Scholar
- 21.B. C. Paul, A. Raychowdhury, and K. Roy, “Device operation for digital subthreshold logic operation,” IEEE Trans. Electron Dev., 52 (2), 237–247, 2005.CrossRefGoogle Scholar
- 22.S. Chakraborty, A. Mallik, C. K. Sarkar, and V. R. Rao, “Impact of halo doping on the subthreshold performance of deep-submicron CMOS devices and circuits for ultra-low power analog/mixed-signal applications,” IEEE Trans. Electron Dev., 54 (2), 241–247, 2007.CrossRefGoogle Scholar
- 23.R. W. Berry, P. M. Hall, and M. T. Harris, Thin Film Technology, Van Nostrand, 1968.Google Scholar
- 24.W.-C. Liu, K.-B. Thei, H.-M. Chuang, K.-W. Lin, C.-C. Cheng, Y.-S. Ho, C.-W. Su, S.-C. Wong, C.-H. Lin, and C. H. Diaz, “Characterization of polysilicon resistors in sub-0.25μm CMOS ULSA applications,” IEEE Electron Dev. Lett., 22 (7), 318–320, 2001.CrossRefGoogle Scholar
- 25.J. Y. Seto, “The electrical properties of polycrystalline silicon films,” J. Appl. Phys., 46 (12), 5247–5254, 1975.CrossRefGoogle Scholar
- 26.N. C.-C. Lu, L. Gerzberg, C.-Y. Lu, and J. D. Meindl, “Modeling and optimization of monolithic polycrystalline silicon resistors,” IEEE Trans. Electron Dev., ED-28 (7), 818– 830, 1981.CrossRefGoogle Scholar
- 27.M. M. Mandurah, K. C. Saraswat, and T. I. Kamins, “Phosphorus doping of low pressure chemically vapor-deposited silicon films,” J. Electrochem. Soc., 126 (8), 1019–1023, 1979.CrossRefGoogle Scholar
- 28.N. C. C. Lu, L. Gerzberg, and J. D. Meindl, “A quantitative model of the effect of grain size on the resistivity of polycrystalline silicon resistors,” Electron Dev. Lett., EDL-1 (3), 38–41, 1980.CrossRefGoogle Scholar
- 29.T. I. Kamins, “Hall mobility in chemically deposited polycrystalline silicon,” J. Appl. Phys., 42 (11), 4357–4365, 1971.CrossRefGoogle Scholar
- 30.M. E. Cowher and T. O. Sedgwick, “Chemical vapor deposited polycrystalline silicon,” J. Electrochem. Soc., 119 (11), 1565–1570, 1972.CrossRefGoogle Scholar
- 31.A. L. Fripp, “Dependence of resistivity on the doping level of polycrystalline silicon,” J. Appl. Phys., 46 (3), 1240–1244, 1975.CrossRefGoogle Scholar
- 32.P. Rai-Choudhury and P. L. Hower, “Growth and characterization of polycrystalline silicon,” J. Electrochem. Soc., 120 (12), 1761–1766, 1971.CrossRefGoogle Scholar
- 33.G. Baccarani and B. Riccò, “Transport properties of polycrystalline silicon films,” J. Appl. Phys., 49 (11), 5565–5570, 1978.CrossRefGoogle Scholar
- 34.M. Nakabayshi, M. Ikegami, and T. Daikoku, “Influence of hydrogen on electrical characteristics of poly-Si resistor,” Jpn. J. Appl. Phys., 32, Part 1 (9A), 3734–3738, 1993.CrossRefGoogle Scholar
- 35.F. Hegner, “The industrial production of high quality nickel-chromium resistors with controlled temperature coefficient of resistance,” Thin Solid Films, 57 (2), 359–362, 1979.CrossRefGoogle Scholar
- 36.G. Nocerino and K. E. Singer, “The electrical and compositional structure of thin Ni-Cr films,” Thin Solid Films, 57 (2), 343–348, 1979.CrossRefGoogle Scholar
- 37.M. A. Bayne, “Al-doped Ni-Cr for temperature coefficient of resistance control in hybrid thin-film resistors,” J. Vac. Sci. Technol. A4 (6), 3142–3145, 1986.Google Scholar
- 38.F. Wu, A. W. McLaurin, K. E. Henson, D. G. Managhan, and S. L. Thomasson, “The effects of the process parameters on the electrical and microstructure characteristics of the CrSi thin resistor films: part I,” Thin Solid Films, 332, 418–422, 1998.CrossRefGoogle Scholar
- 39.D. Nachrodt, U. Pachen, A. Ten Have, and H. Vogt, “Ti/Ni(80%)Cr(20%) thin-film resistor with a near zero temperature coefficient of resistance for integration in a standard CMOS process,” IEEE Electron Dev. Lett., 29 (3), 212–214, 2008.CrossRefGoogle Scholar
- 40.P. Zurcher, P. Alluri, P. Chu, A. Duvallet, C. Happ, R. Henderson, J. Mendonca, M. Kim, M. Petras, M. Raymond, T. Remmel, D. Roberts, B. Steimle, J. Stipanuk, S, Straub, T. Sparks, M. Tarabbia, H. Thibieroz, and M. Miller, “Integration of thin film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologies,” IEEE IEDM Tech. Dig., 153–156, 2000.Google Scholar
- 41.P. Fehlhaber, “Laser trimming of SiCr thin-film resistors,” IEEE IEDM Tech. Dig., 9–10, 1969.Google Scholar
- 42.R. H. Wagner, “Functional laser trimming: An overview,” Laser Processing of Semiconductors and Hybrids, SPIE Proceedings, 611, 8–17, 1986.Google Scholar
- 43.M. J. Mueller and W. Mickanin, “Functional laser trimming of thin film resistors on silicon IC,” Laser Processing of Semiconductors and Hybrids, SPIE Proceedings, 611, 70–83, 1986.Google Scholar
- 44.H.-M. Chuang, K.-B. Thei, S.-F. Tsai, and W.-X. Liu, “Temperature-dependent characteristics of polysilicon and diffused resistors,” IEEE Trans. Electron Dev., 50 (5), 1413– 1415, 2003.CrossRefGoogle Scholar
- 45.W. A. Lane and G. T. Wrixon, “The design of thin-film polysilicon resistors for analog IC applications,” IEEE Trans. Electron Dev., 36 (4), 738–744, 1989.CrossRefGoogle Scholar
- 46.D. W. Lee, T. M. Roh, H. S. Park, J. Kim, J. G. Koo, and D. Y. Kim, “Fabrication technology of polysilicon resistors using novel mixed process for analogue CMOS application,” IEEE Electron Lett., 35 (7), 803–804, 1999.Google Scholar
- 47.M. S. Raman, T. Kifle, E. Bhattacharya, and K. N. Bhat, “Physical model for the resistivity and temperature coefficient of resistivity in heavily doped polysilicon,” IEEE Trans. Electron Dev., 53 (8), 1885–1892, 2006.CrossRefGoogle Scholar
- 48.P. Steinmann, S. M. Stuart, R. Higgins, “Controlling the TCR of thin film resistors,” Euro. Dev. Res. Conf., 451–453, 2000.Google Scholar
- 49.C. A. Neugebauer and M. B. Webb, “Electrical conduction mechanism in ultrathin, evaporated metal films,” J. Appl. Phys., 33, 74–82, 1962.CrossRefGoogle Scholar
- 50.J. R. Sambles and T. W. Preist, “The effects of surface scattering upon resistivity,” J. Phys. F: Met. Phys., 12, 1971–1987, 1982.CrossRefGoogle Scholar
- 51.Y. Amemiya, T. Ono, and K. Kato, “Electrical trimming of heavily doped polycrystalline silicon resistors,” IEEE Trans. Electron Dev., ED-26 (11), 1738–1742, 1979.CrossRefGoogle Scholar
- 52.K. Kato, T. Ono, and Y. Amemiya, “A physical mechanism of current-induced resistance decrease in heavily doped polysilicon resistors,” IEEE Trans. Electron Dev., ED-29 (8), 1156–1161, 1982.CrossRefGoogle Scholar
- 53.S. Das and S. K. Lahiri, “Electrical trimming of ion-beam-sputtered polysilicon resistors by high current pulses,” IEEE Trans. Electron Dev., 41 (8), 1429–1434, 1994.CrossRefGoogle Scholar
- 54.C. T. Black, K. W. Guarini, Y. Zhang, H. Kim, J. Benedict, E. Sikorski, I. V. Babich, and K. R. Milkove, “High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitor,” IEEE Electron Dev. Lett., 25 (9), 622–624, 2004.CrossRefGoogle Scholar
- 55.T.-I. Liou and C.-S. Teng, “n+-poly-to-n+-silicon capacitor structure for single poly analog CMOS and BiCMOS process,” IEEE Trans. Electron Dev., 36 (9), 1620–1628, 1989.CrossRefGoogle Scholar
- 56.S. A. St Onge, S. G. Franz, A. F. Puttlitz, A. Kalinoski, B. E. Johnson, and B. El-Kareh, “Design of precision capacitors for analog applications,” IEEE Trans. Comput. Hybrids Manuf. Tech., 15 (6), 1064–1070, 1992.CrossRefGoogle Scholar
- 57.J. L. McCreary, “Matching properties, and voltage and temperature dependence of MOS capacitors,” IEEE J. Solid-State Circuits, SC-14 (6), 608–616, 1987.Google Scholar
- 58.C. Kaya, H. Tigelaar, J. Peterson, M. De Wit, J. Fattaruso, D. Hester, S. Kiriaki, K.-S. Tan, and F. Tsay, “Polycide/metal capacitors for high precision A/D converters,” IEEE IEDM Tech. Dig., 782–785, 1988.Google Scholar
- 59.J. A. Babcock, S. G. Balster, A. Pinto, C. Dirnecker, P. Steinmann, R. Jumpertz, and B. El-Kareh, “Analog characteristics of metal-insulator-metal capacitors using PECVD nitride dielectrics,” IEEE Trans. Electron Dev., 22 (5), 230–232, 2001.CrossRefGoogle Scholar
- 60.K. Stein, G. Hueckel, E. Eld, T. Bartush. R. Groves, N. Greco, and D. Harame, “High reliability metal insulator metal capacitors for silicon germanium analog applications,” IEEE BCTM Tech. Dig., 191–194, 1997.Google Scholar
- 61.T. Yoshitomi, Y. Ebuchi, H. Kimijima, T. Ohguro, E. Morifuji, H. S. Momose, K. Kasai, K. Ishimaru, F. Matsuoka, Y. Katsumata, M. Kinugawa, and H. Iwai, “High performance MIM capacitor for RF BiCMOS/CMOS LSI,” IEEE BCTM Tech. Dig., 133–136, 1999.Google Scholar
- 62.T. Ishikawa, D. Kodama, Y. Matsui, M. Hiratani, T. Furusawa, and D. Hisamoto, “High-capacitance Cu/Ta
_{2}O_{5}/Cu MIM structure for SoC applications featuring a single-mask addon process,” IEEE IEDM Tech. Dig., 940–942, 2002.Google Scholar - 63.C. Zhu, H. Hu, X. Yu, S. J. Kim, A. Chin, M. F. Li, B. J. Cho, and D.-L. Kwong, “Voltage and temperature dependence of capacitance of high-K HfO
_{2}MIM capacitors: A unified understanding and prediction,” IEEE IEDM Tech. Digest, 879–882, 2003.Google Scholar - 64.H. Hu, S.-J. Ding, H. F. Lim, C. Zhu, M. F. Li, S. J. Kim, X. F. Yu, J. H. Chen, Y. F. Yong, B. J. Cho, D. S. H. Chan, S. C. Rustagi, M. B. Yu, C. H. Tung, A. Du, D. My, P. D. Foo, A. Chin, and D.-L. Kwong, “High performance ALD HfO
_{2}-Al_{2}O_{3}laminate MIM capacitor for RF and mixed signal IC applications,” IEEE IEDM Tech. Dig., 379–382, 2003.Google Scholar - 65.S. J. Kim, B. J. Cho, M. B. Yu, M.-F. Li, Y.-Z. Xiong, C. Zhu, A. Chin, and D.-M. Kwong, “Metal-insulator-metal RF bypass capacitor using niobium oxide (Nb
_{2}O_{5}) with HfO_{2}/Al_{2}O_{3}barriers,” IEEE Electron Dev. Lett., 26 (9), 625–627, 2005.CrossRefGoogle Scholar - 66.K. C. Chiang, C.-C. Huang, G. L. Chen, W. J. Chen, H. L. Kao, Y.-H. Wu, A. Chin, and S. P. McAlister, “High performance SrTiO
_{3}MIM capacitors for analog applications,” IEEE Trans. Electron Dev., 53 (9), 2312–2319, 2006.CrossRefGoogle Scholar - 67.K. Hyyppä, “Dielectric absorption in memory capacitors,” IEEE Trans. Instrum. Meas., 21 (1), 53–56, 1972.CrossRefGoogle Scholar
- 68.J. C. Kuenen and G. C. M. Meijer, “Measurement of dielectric absorption of capacitors and analysis of its effects on VCO,” IEEE Trans. Instrum. Meas., 45 (1), 89–97, 1996.CrossRefGoogle Scholar
- 69.C. Iorga, “Compartmental analysis of dielectric absorption in capacitors,” IEEE Trans. Dielectrics, 7 (2), 187–192, 2000.CrossRefGoogle Scholar
- 70.P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE J. Solid-State Circuits, 35 (6), 905–910, 2000.CrossRefGoogle Scholar
- 71.J. Maget, R. Kraus, and M. Tiebout, “A physical model of a CMOS varactor with high capacitance tuning range and its application to simulate integrated VCOs,” Solid-State Electron, 46, 1609–1615, 2002.CrossRefGoogle Scholar
- 72.C.-S. Chang, C.-P. Chao, J. G. J. Chern, and J. Y.-C. Sun, “Advanced CMOS technology portfolio for RF IC applications,” IEEE Trans. Electron Dev., 52 (7), 1324–1334, 2005.CrossRefGoogle Scholar
- 73.B. El-Kareh, S. Balster, W. Leitz, P. Steinmann, H. Yasuda, M. Corsi, K. Dawoodi, C. Dirnecker, P. Foglietti, A. Haeusler, P. Menz, M. Ramin, T. Scharnagl, M. Schiekofer, M. Schober, U. Schulz, L. Swanson, D. Tatman, M. Waitschull, J. W. Weijtmans, and C. Willis, “A 5V complementary-SiGe BiCMOS technology for high-speed precision analog circuits,” IEEE BCTM, 211–214, 2003.Google Scholar
- 74.Y. Morandini, J.-F. Larchanchel, and C. Gaquiere, “Evaluation of SiGeC HBT varactor using different collector access and base-collector junction configuration in BiCMOS technologies,” IEEE BCTM Tech. Dig., 246–249, 2007.Google Scholar
- 75.R. A. Moline and G. F. Foxhall, “Ion-implanted hyperabrupt junction voltage variable capacitors,” IEEE Trans. Electron Dev., ED-19 (2), 267–273, 1972.CrossRefGoogle Scholar
- 76.S. M. Sze, Properties of Semiconductor Devices, John Wiley & Sons, 1981.Google Scholar
- 77.P. J. Kannam, S. Ponczak, and J. Olmstead, “Design considerations of hyperabrupt varactor diodes,” IEEE Trans. Electron Dev., ED-18 (3), 109–115, 1971.CrossRefGoogle Scholar
- 78.M. H. Norwood and E. Shatz, “Voltage variable capacitor tuning: A review,” Proc. IEEE, 56 (5), 788–798, 1968.CrossRefGoogle Scholar
- 79.T. Soorapanth, C. P. Yue, D. K. Shaeffer, T. H. Lee, and S. S. Wong, “Analysis and optimization of accumulation-mode varactor for RF ICs,” IEEE Symp. VLSI Circuits Tech. Dig., 32–33, 1998.Google Scholar
- 80.F. Svelto, P. Erratico, S. Manzini, and R. Castello, “A metal-oxide-semiconductor varactor,” IEEE Electron Dev. Lett., 20 (4), 164–166, 1999.CrossRefGoogle Scholar
- 81.F. Svelto, S. Manzini, and R. Castello, “A three terminal varactor for RF IC's in standard CMOS technology,” IEEE Trans. Electron Dev., 47 (4), 893–895, 2000.CrossRefGoogle Scholar
- 82.W. M. Y. Wong, P. S. Hui, Z. Chen, K. Shen, J. Lau, P. C. H. Chan, and P.-K. Ko, A wide tuning range gated varactor,” IEEE J. Solid-State Circuits, 35 (5), 773–779, 2000.CrossRefGoogle Scholar
- 83.J.-H. Gau, R.-T. Wu, Steven Sang, C.-H. Kuo, T.-L. Chang, H.-H. Chen, A. Chen, and J. Ko, “Gate-assisted high-Q-factor junction varactor,” IEEE Electron Dev. Lett., 26 (9), 682– 683, 2005.CrossRefGoogle Scholar
- 84.Y.-J. Chan, C.-F. Huang, C.-C. Wu, C.-H. Chen, and C.-P. Chao, “Performance consideration of MOS and junction diodes for varactor application,” IEEE Trans. Electron Dev., 54 (9), 2570–2573, 2007.CrossRefGoogle Scholar
- 85.J.-B. Shyu, G. C. Temes, and F. Krummenacher, “Random error effects in matched MOS capacitors and current sources,” IEEE J. Solid-State Circuits, SC-17, 1070–1076, 1982, and SC-19 (6), 948–955, 1984.CrossRefGoogle Scholar
- 86.K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, “Characterization and modeling of mismatch in MOS transistor5s for precision analog design,” IEEE J. Solid-State Circuits, SC-21 (6), 1057–1066, 1986.CrossRefGoogle Scholar
- 87.M. J. M. Pelgrom, A. C. J., Duinmaijer, and A. P. G., Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, 24 (5), 1433–1440, 1989.CrossRefGoogle Scholar
- 88.P. R. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,” IEEE J. Solid-State Circuits, 40 (6), 1212–1224, 2005.CrossRefGoogle Scholar
- 89.M. J. M. Pelgrom, H. P. Tuinhout, and M. Vertregt, “Transistor matching in analog CMOS applications,” IEEE IEDM Tech. Dig., 915–918, 1998.Google Scholar
- 90.S. Lovett, M. Welten, A. Mathewson, and B. Mason, “Optimizing MOS transistor matching,” IEEE J. Solid-State Circuits, 33 (1), 147–150, 1998.CrossRefGoogle Scholar
- 91.G. Baccarani, M. Severi, and G. Soncini, “A new method for the determination of the interfaced-state density in the presence of statistical fluctuation of the surface potential,” Appl. Phys. Lett., 23 (5), 265–267, 1973.CrossRefGoogle Scholar
- 92.R. Castagne and A. Vapaille, “Apparent interface state density introduced by the spatial fluctuations of surface potential in an M.O.S. structure,” Electron Lett., 6 (22), 691–693, 1970.CrossRefGoogle Scholar
- 93.R. W. Keyes, “Physical limits in digital electronics,” Proc. IEEE, 740–768, 1975.Google Scholar
- 94.B. Hoeneisen and C. A. Mead, “Fundamental limits in microelectronics – I. MOS technology,” Solids-State Electron., 819–829, 1972.Google Scholar
- 95.K. Takeuchi, T. Tatsumi, and A. Furukawa, “Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation,” IEEE IEDM Tech. Dig., 841–844, 1997.Google Scholar
- 96.P. A. Stolk and D. B. M. Klaassen, “The effect of statistical dopant fluctuations on MOS device performance,” IEEE IEDM Tech. Dig., 627–630, 1996.Google Scholar
- 97.T. Mizuno, J.-I. Okamura, and A. Toriumi, “Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs,” IEEE Trans. Electron Dev., 41 (11), 2216–2221, 1994.CrossRefGoogle Scholar
- 98.A. Asenov and S. Saini, “Polysilicon gate enhancement of the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFETs with ultrathin gate oxide,” IEEE Trans. Electron Dev., 47 (4), 805–812, 2000.CrossRefGoogle Scholar
- 99.H. P. Tuinhout, A. H. Montree, and P. A. Stolk, “Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors,” IEEE IEDM Tech. Dig., 631–634, 1997.Google Scholar
- 100.R. Difrenza, J. C. Vildeuil, P. Llinares, and G. Ghibaudo, “Impact of grain number fluctuations in the MOS transistor gate on matching performance,” IEEE ICMTS, 244–249, 2003.Google Scholar
- 101.H. Ryssel, H. Iberl, M. Bleier, G. Prine, K. Haberger, and H. Kranz, “Arsenic-implanted polysilicon layers,” Appl. Phys., 24 (3), 197–200, 1981.CrossRefGoogle Scholar
- 102.B. Swaminathan, K. C. Saraswat, and R. W. Dutton, “Diffusion of arsenic in polycrystalline silicon,” Appl. Phys. Lett., 40 (9), 795–798, 1982.CrossRefGoogle Scholar
- 103.M. Arienzo, Y. Komem, and A. E. Michel, “Diffusion of arsenic in bilayer polycrystalline silicon films,” J. Appl. Phys., 55 (2), 365–369, 1984.CrossRefGoogle Scholar
- 104.H. Schaber, R. V. Criegern, and I. Weitzel, “Analysis of polycrystalline diffusion source by secondary ion mass spectroscopy,” J. Appl. Phys., 58 (11), 4036–4042, 1985.CrossRefGoogle Scholar
- 105.J. M. C. Stork, M. Arienzo, and C. Y. Wong, “Correlation between the diffusive and electrical barrier properties of the interface in polysilicon contacted n+-p junctions,” IEEE Trans. Electron Dev., 32, 1766–1770, 1985.CrossRefGoogle Scholar
- 106.J. L. Hoyt, E. F. Crabbé, R. F. W. Pease, J. F. Gibbons, and A. F. Marshall, “Lateral uniformity of n+/p junctions formed by arsenic diffusion from epitaxially aligned polycrystalline silicon on silicon”, J. Electrochem. Soc., 135 (7), 1773–1779, 1988.CrossRefGoogle Scholar
- 107.S. Nédèle, D. Mathiot, and M. Gaunneau, “Diffusion of boron on polycrystalline silicon,” ESSDERC Tech. Dig., 153–156, 1996.Google Scholar
- 108.A. Wang and K. C. Saraswat, “A strategy for modeling of variations due to grain size in polycrystalline thin-film transistors,” IEEE Trans. Electron Dev., 47 (5), 1035–1043, 2000.CrossRefGoogle Scholar
- 109.J. T. Horstmann, U. Hilleringmann, and K. F. Goser, “Matching analysis of deposition defined 50-nm MOSFETs,” IEEE Trans. Electron Dev., 45 (1), 299–306, 1998.CrossRefGoogle Scholar
- 110.S. Winkelmeier, M. Sarstedt, M. Ereken, M. Goethals, and K. Ronse, “Metrology method for the correlation of line edge roughness for different resists before and after etch,” Microelec-tron. Eng., 57–58, 665–672, 2001.Google Scholar
- 111.S. Xiong and J. Bokor, “A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices,” IEEE Trans. Electron Dev., 51 (2), 228–232, 2004.CrossRefGoogle Scholar
- 112.L. H. A. Leunissen, M. Ercken, and G. P. Patsis, “Determining the impact of statistical fluctuations on resist line edge roughness,” Microelectron. Eng., 78–79, 2–10, 2005.CrossRefGoogle Scholar
- 113.C. H. Diaz, H.-J. Tao, Y.-C. Ku, A. Yen, and K. Young, “An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling,” IEEE Electron Dev. Lett., 22 (6), 287–289, 2001.CrossRefGoogle Scholar
- 114.T. Linton, M. Chandhok, B. J. Rice, and C. Schrom, “Determination of the line edge roughness specification for 34 nm devices,” IEEE IEDM Tech. Dig., 303–306, 2002.Google Scholar
- 115.J. A. Croon, G. Storms, S. Winkelmeier, I. Pollentier, M. Ercken, S. Decoutere, W, Sansen, and H. E. Maes, “Line edge roughness: Characterization, modeling and impact on device behavior,” IEEE IEDM Tech. Dig., 307–310, 2002.Google Scholar
- 116.G. Declerck, “A look into the future of nanoelectronics,” Symp. VLSI Tech. Dig., 6–10, 2005.Google Scholar
- 117.M. Steyart, J. Bastos, R. Roovers, P. Kinget, W. Samsen, B. Graindourze, A. Pergoot, and Er. Janssens, “Threshold voltage mismatch in short-channel MOS transistors,” Electron. Lett., 30 (18), 146–148, 1994.Google Scholar
- 118.S.-C. Chyi, K.-H. Pan, and D.-J. Ma, “A CMOS mismatch model and scaling effects,” IEEE Electron Dev. Lett., 18 (6), 261–263, 1997.CrossRefGoogle Scholar
- 119.P. H. Drennan and C. C. McAndrew, “A comprehensive MOSFET mismatch model,” IEEE IEDM Tech. Dig., 167–170, 1999.Google Scholar
- 120.P. G. Brennan and V. C. McAndrew, “Understanding MOSFET mismatch for analog design,” IEEE J. Solid-State Circuits, 38 (3), 450–456, 2003.CrossRefGoogle Scholar
- 121.T. Serrano-Gotarredona and B. Linares-Barranco, “A new five-parameter MOS transistor mismatch model,” IEEE Electron Dev. Lett., 21 (1), 37–39, 2000.CrossRefGoogle Scholar
- 122.H. Klimach, A. Arnaud, C. Galup-Montoro, and M. C. Schneider, “MOSFET mismatch modeling: A new approach,” IEEE Des. Test Comput., 23 (1), 20–29, 2006.CrossRefGoogle Scholar
- 123.A. R. Brown, G. Roy, and A. Asenov, “Poly-Si-gate-related variability in decananome-ter MOSFETs with conventional architecture,” IEEE Trans. Electron Dev., 54 (11), 3036– 3063, 2007.Google Scholar
- 124.H. Tuinhout, M. Pelgrom, R. Penning de Vries, and M. Vertregt, “Effects of metal coverage on MOSFET matching,” IEEE IEDM Tech. Dig., 735–738, 1997.Google Scholar
- 125.J. A. Croon, H. P. Tuinhout, R. Difrenza, J. Knol, A. J. Moonen, S. Decoutere, H. E. Maes, and W. Sansen, “A comparison of extraction techniques for threshold voltage mismatch,” Proc. IEEE 2002 Conf. Microelectronics Test Structures, 15, 225–240, 2002.Google Scholar
- 126.P. G. Drennan, C. C. McAndrew, J. Bates, and D. Schroder, “Rapid evaluation of the root causes of BJT mismatch,” Proc. International Conf. on Microelectronic Test Structures (ICMTS), 122–127, 2000.Google Scholar
- 127.P. G. Drennan, C. C. McAndrew, and J. Bates, “A comprehensive vertical BJT mismatch model,” IEEE BCTM Tech. Dig., 83–86, 1998.Google Scholar
- 128.H. P. Tuinhout, “Improving BiCMOS technologies using BJT parametric mismatch characterization,” IEEE BCTM Tech. Dig., 163–170, 2003.Google Scholar
- 129.C. C. McAndrew, J. Bates, T. T. Ida, and P. Drennan, “Efficient statistical BJT modeling, why β is more than I
_{C}/I_{B},” IEEE BCTM Tech. Dig., 28–31, 1997.Google Scholar - 130.S. Bordez, S. Danaie, R. Difrenza, J.-C. Vildeuil, and G. Morin, “Study of bipolar matching at high current level with various test configurations leading to a new model approach,” IEEE BCTM Tech. Dig., 62–65, 2005.Google Scholar
- 131.P. G. Drennan,“Diffused resistor mismatch modeling and characterization,” IEEE BCTM Tech. Dig., 27–30, 1999.Google Scholar
- 132.R. Thewes, R. Brederlow, C. Dahl, U. Kollmer, C. G. Linnenbank, B. Holzapfl, J. Becker, J. Kissing, S. Kessel, and W. Weber, “Explanation and quantitative model for the matching behavior of poly-silicon resistors,” IEEE IEDM Tech. Dig., 771–774, 1998.Google Scholar
- 133.H. Thibieroz, P. Shaner, and Z. C. Butler, “Mismatch and flicker noise characterization of tantalum nitride thin film resistors for wireless applications,” IEEE ICMTS, 14, 207–212, 2001.Google Scholar
- 134.U. Grünebaum, J. Oehm, and K. Schumacher, “Mismatch Modeling and Simulation – A Comprehensive Approach,” Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, 29, 165–171, 2001.CrossRefGoogle Scholar
- 135.H. Iwai and S. Kohyama, “On-chip capacitance measurement circuits in VLSI structures,” IEEE Trans. Electron Dev., ED-29 (10), 1622–1626, 1982.CrossRefGoogle Scholar
- 136.B. Eitan, “Channel-length measurement technique based on a floating-gate device,” IEEE Electron Dev. Lett., 9 (7), 340–342, 1988.CrossRefGoogle Scholar
- 137.C. Kortekaas, “On-chip quasi-static floating-gate capacitance measurement method,” IEEE ICMTS, 3, 109–113, 1990.Google Scholar
- 138.H. P. Tuinhout, H. Elzinga, J. T. Brugman, and F. Postma, “Accurate capacitor matching measurements using floating gate test structures,” IEEE ICMTS, 8, 133–137, 1995.Google Scholar
- 139.H. P. Tuinhout, H. Elzinga, J. T. Brugman, and F. Postma, “The floating gate measurement technique for characterization of capacitor matching,” IEEE Trans. Semicon. Manuf., 9 (1), 2–8, 1996.CrossRefGoogle Scholar
- 140.J. Hunter, P. Gudem, and S. Winters, “A differential floating gate capacitance mismatch measurement technique,” IEEE ICMTS, 13, 142–147, 2000.Google Scholar
- 141.A. van der Ziel, Noise in Solid State Devices and Circuits, John Wiley & Sons, 1986.Google Scholar
- 142.M. von Haartman and M. Ö stling, Low-Frequency Noise in Advanced NOS Devices, Springer, 2007.Google Scholar
- 143.C. Surya and T. Y.Hsiang, “Surface mobility fluctuations in metal-oxide-semiconductor field-effect transistors,” Phys. Rev. B., 35 (12), 6343–6347, 1987.CrossRefGoogle Scholar
- 144.K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “Random telegraph noise of deep-submicrometer MOSFETs,” IEEE Electron Dev. Lett., 11 (2), 90–92, 1990.CrossRefGoogle Scholar
- 145.K. S. Ralls, W. J. Skocpol, L. D. Jackel, R. E. Howard, L. A. Fetter, R. W. Epworth, and D. M. Tennant, “Discrete resistance switching in submicrometer silicon inversion layers: Individual interface traps and low-frequency (1/f?) noise,” Phys. Rev. Lett., 52 (3), 228–231, 1984.CrossRefGoogle Scholar
- 146.M. J. Uren, D. J. Day, and M. J. Kirton, “1/f and random telegraph noise in silicon metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., 47 (11), 1195–1197, 1985.CrossRefGoogle Scholar
- 147.M. J. Kirton, M. J. Uren, and S. Collins, “Individual interface states and their implication for low-frequency noise in MOSFETs,” Appl. Surf. Science, 30 (1–4), 148–152, 1987.CrossRefGoogle Scholar
- 148.Y. F. Lim, Y. Z. Xiong, N. Singh, R. Yang, Y. Jiang, D. S. H. Chan, W. Y. Loh, L. K. Bera, G. Q. Lo, N. Balasubramanian, and D. -L. Kwong, “Random telegraph signal noise in gate-all-around Si-FinFET with ultra-narrow body,” IEEE Trans. Electron Dev., 77 (9), 765– 768, 2006.Google Scholar
- 149.S.-R. Li, W. McMahon, Y.-L. R. Lu, and Y.-H. Lee, “RTS noise characterization in flash cells,“IEEE Electron Dev. Lett., 29 (1), 106–108, 2008.CrossRefGoogle Scholar
- 150.C. M. Compagnoni, R. Gusmeroli, A. S. Spinelli, and A. Visconti, “RTN VT instability from the stationary trap-filling condition: An analytical spectroscopic investigation,” IEEE Trans. Electron. Dev., 55 (2), 655–661, 2008.CrossRefGoogle Scholar
- 151.R. H. Howard, W. J. Skocpol, L. D. Jackel, P. M. Mankiewich, L. A. Fetter, D. M. Tennant, R. Epworth, and K. S. Ralls, “Single electron switching events in nanometer-scale Si MOS-FETs,” IEEE Trans. Electron Dev., ED-32 (9), 1669–1674, 1985.CrossRefGoogle Scholar
- 152.S. Machlup, “Noise in semiconductors: Spectrum of a two-parameter random signal,” J. Appl. Phys., 25, 241–243, 1954.CrossRefGoogle Scholar
- 153.R. C. Jaeger and A. J. Broderson, “Low-frequency noise sources in bipolar junction transistors,” IEEE Trans. Electron Dev., ED-17 (2), 128–134, 1970.CrossRefGoogle Scholar
- 154.J. L. Plumb and E. R. Chenette, “Flicker noise in transistors,” IEEE Trans. Electron Dev., 10 (5), 304–308, 1963.CrossRefGoogle Scholar
- 155.O. Roux dit Buisson and G. Moria, “Flicker noise characteristics of polysilicon resistors in submicron BiCMOS technologies,” IEEE ICMTS, 10, 49–51, 1997.Google Scholar
- 156.E. Zhao, R. Krithivasan, A. K. Sutton, Z. Jin, J. D. Cressler, B. El-Kareh, S. Balster, and H. Yasuda, “An investigation of low-frequency noise in complementary SiGe HBTs,” IEEE Trans. Electron Dev., 53 (2), 329–338, 2006.CrossRefGoogle Scholar