Advertisement

Insulated-Gate Field-Effect Transistor

A field-effect transistor consists of four terminals: gate, source, drain and body or substrate (Fig. 5.1). The field created by a voltage applied to a gate modulates the resistance of region under the gate between source and drain. The modulated region of the transistor body is referred to as the channel. There are three types of field-effect transistors shown in Fig. 5.1, of which the MOSFET is one. In a MOSFET, the gate consists of an MOS structure that slightly overlaps two junctions located on either side of the gate. The source and drain are of opposite polarity to the body. This type of transistor is also known as an insulated field-effect transistor, IGFET, because the gate is separated from the body by an insulator. In a junction field-effect transistor or JFET, one or two pn junctions act as the gate that modulates the width of a conductive path between the source and drain. The source and drain are of the same polarity type as the body. A metal-semiconductor field-effect transistor, or MESFET, operates similarly to a JFET, except that the gate consists of a Schottky-barrier diode formed between a metal in contact with the semiconductor

This chapter focuses on the MOSFET which is by far the most common. The discussion of a JFET follows in the next chapter

Keywords

Threshold Voltage Gate Voltage Dynamic Random Access Memory Metal Gate Equivalent Oxide Thickness 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    A. S. Grove and D. J. Fitzgerald,“Surface effects on pn junctions–Characteristics of surface space-charge regions under non-equilibrium conditions,”Solid-State Electron.,9(8),783–806,1966.Google Scholar
  2. 2.
    R. N. Hall,“Electron-hole recombination in germanium,”Phys. Rev.,87(2),387–394,1952.Google Scholar
  3. 3.
    W. Shockley and W. T. Read,“Statistics of recombination of holes and electrons,”Phys. Rev.,85(5),835–842,1952.Google Scholar
  4. 4.
    W. P. Noble,S. H. Voldman,and A. Bryant,“The effects of gate field on the leakage characteristics of heavily doped junctions,”IEEE Trans. Electron Dev.,36(4),720–726,1989.Google Scholar
  5. 5.
    W. Shockley,“Problems related to p-n junctions in silicon,”Solid-State Electron.,2(1),35–67,1961.Google Scholar
  6. 6.
    J. F. Verwey,R. P. Kramer,and B. J. de Maagt,“Mean free path of hot electrons at the surface of boron-doped silicon,”J. Appl. Phys.,46(6),2612–2619,1975.Google Scholar
  7. 7.
    B. El-Kareh,“Effect of surface field on junction avalanche breakdown,”IEDM Tech. Digest.,11–14,1972.Google Scholar
  8. 8.
    J. L. Moll,Physics of Semiconductor Devices,McGraw Hill,Chap. 9,1964.Google Scholar
  9. 9.
    E. G. Kane,“Theory of tunneling,”J. Appl. Phys.,32(1),83–91,1961MATHMathSciNetGoogle Scholar
  10. 10.
    C. Chang and J. Lien,“Corner-field induced drain leakage in thin oxide MOSFETs,”IEDM Tech. Dig.,714–717,1987.Google Scholar
  11. 11.
    T. Y. Chan,J. Chen,P. K. Ko,and C. Hu,“The impact of gate-induced drain leakage current on MOSFET scaling,”IEDM Tech. Dig.,718–721,1987.Google Scholar
  12. 12.
    J. Chen. T. Y. Chan. I. C. Chen,P. K. Ko,and C. Hu,“Sub-breakdown drain leakage current in MOSFET,”IEEE Electron. Dev. Lett.,8(11),515–517,1987.Google Scholar
  13. 13.
    H. K. J. Ihantola and J. L. Moll,“Design theory of a surface field-effect transistor,”Solid-State Electron.,7(6) 423,1964.Google Scholar
  14. 14.
    C. T. Sah,“Characteristics of the metal-oxide-semiconductor transistors,”IEEE Trans. Electron Dev.,ED-11(7) 324–345,1964.Google Scholar
  15. 15.
    F. H. Gaensslen,V. L. Rideout,E. J. Walker,and J. J. Walker,“Very small MOSFETs for low-temperature operation,”IEEE Trans. Electron Dev.,ED-24(3),218–229,1977.Google Scholar
  16. 16.
    J. R. Schriefer,“Effective carrier mobility on surface space charge layers,”Phys. Rev.,97,641–646,1955.Google Scholar
  17. 17.
    F. Fang and S. Triebwasser,“Carrier surface scattering in silicon inversion layers,”IBM J. Res. Dev.,8,410–415,1964.Google Scholar
  18. 18.
    F. Stern and W. E. Howard,“Properties of semiconductor surface inversion layers in the electric quantum limit,”Phys. Rev. B,163,816–835,1967.Google Scholar
  19. 19.
    F. F. Fang and A. B. Fowler,“Transport properties of electrons in inverted silicon surface,”Phys. Rev.,169,616–631,1968.Google Scholar
  20. 20.
    V. G. K. Reddi,“Majority carrier surface mobilities in thermally oxidized silicon,”IEEE Trans. Electron Dev.,ED-15(3),151–160,1968.Google Scholar
  21. 21.
    C.-T. Sah,T. H. Ning,and L. L. Tschopp,“The scattering of electrons by surface oxide charge and by lattice vibrations,”Surf. Sci.,32,561–575,1972.Google Scholar
  22. 22.
    T. Nishida and C.-T. Sah,“A physically based mobility model for MOSFET numerical simulations,”IEEE Trans. Electron Dev.,34(2),310–320,1987.Google Scholar
  23. 23.
    H. Shin,G. M. Yeric,A. F. Tasch,and C. M. Maziar,“Physically based models for effective mobility and local field mobility of electrons in MOS inversion channels,”Solid-State Electron.,34(6),545–552,1991.Google Scholar
  24. 24.
    S.-I. Tagaki,A. Toriumi,M. Iwase,and H. Tango,“On the universality of inversion layer mobility in silicon MOSFETs Part I – Effect of substrate impurity concentration,”IEEE Trans. Electron. Dev.,41(12),2357–2362,1994.Google Scholar
  25. 25.
    O. Leistiko,A. S. Grove,and C. T. Sah,“Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces,”IEEE Trans. Electron. Dev.,ED-12(5),248–254,1965.Google Scholar
  26. 26.
    J. R. Hauser,“Extraction of experimental mobility data for MOS devices,”IEEE Trans. Electron. Dev.,43(11),1981–1988,1996.Google Scholar
  27. 27.
    A. G. Sabnis and J. T. Clemens,“Characterization of the electron mobility in the inverted <100> surface,”IEEE IEDM Tech. Dig.,18–21,1979.Google Scholar
  28. 28.
    S. C. Sun and J. D. Plummer,“Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,”IEEE Trans. Electron. Dev.,ED-27(8),1497–1508,1980.Google Scholar
  29. 29.
    J. T. Watt and J. D. Plummer,“Universal mobility-field curves for electrons and holes in MOS inversion layers,”VLSI Tech. Dig.,81–82,1987.Google Scholar
  30. 30.
    K. Y. Fu,“Mobility degradation due to the gate field in the inversion layer of MOSFETs,”IEEE Electron. Device Lett.,3(10),292–293,1982.Google Scholar
  31. 31.
    G. Baccarani and G. A. Sai-Halasz,“Spreading resistance in submicron MOSFETs,”IEEE Electron. Device Lett.,4(2),27–29,1983.Google Scholar
  32. 32.
    K. K. Ng and W. T. Lynch,“Analysis of the gate-voltage-dependent series resistance of MOS-FETs,”IEEE Trans. Electron. Dev.,33(7),965–972,1986.Google Scholar
  33. 33.
    K. K. Ng,R. J. Bayruns,and S. C. Fang,“The spreading resistance of MOSFETs,”IEEE Electron. Device Lett.,6(4),195–197,1985.Google Scholar
  34. 34.
    J. M. Pimbley,“Two-dimensional current flow in the MOSFET source-drain,”IEEE Trans. Electron. Dev.,ED-33(7),986–996,1986.Google Scholar
  35. 35.
    International Technology Roadmap for Semiconductors – 2006 update(www.itrs.net).
  36. 36.
    R. H. Dennard,F. H. Gaensslen,V. L. Rideout,E. Bassous,and A. R. LeBlanc,“Design of ion-implanted MOSFET's with very small physical dimensions,”IEEE J. Solid-State Circuits,SC-9,256–268,1974.Google Scholar
  37. 37.
    S.-H. Lo,D. A. Buchanan,Y. Taur,and W. Wang,“Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide NMOSFETs,”IEEE Electron. Device Lett.,18(4),209–211,1997.Google Scholar
  38. 38.
    Y. Taur,S. Wind,Y. J. Mii,Y. Lii,D. Moy,K. A. Jenkins,C. L. Chen,P. J. Coane,D. Klaus,J. Bucchignano,M. Rosenfield,M. G. R. Thompson,and M. Polcari,“High performance 0.1μm CMOS devices with 1.5 V Power Supply,”IEEE IEDM Tech. Dig.,127–130,1993.Google Scholar
  39. 39.
    J. R. Brews,W. Fichtner,E. H. Nicollian,and S. M. Sze,“Generalized guide for MOSFET miniaturization,”IEEE Electron. Device Lett.,EDL-1(1),2–4,1980.Google Scholar
  40. 40.
    W.-H. Lee,T. Osakama,K. Asada,and T. Sugano,“Design methodology and size limitations of submicrometer MOSFETs for DRAM applications,”IEEE Trans. Electron. Dev.,35(11),1876–1884,1988.Google Scholar
  41. 41.
    K. K. Ng,S. A. Eshraghi,and T. D. Stanik,“An improved generalized guide for MOSFET scaling,”IEEE Trans. Electron. Device,40(10),1895–1897,1993.Google Scholar
  42. 42.
    Y. Taur,“CMOS design near the limit of scaling,”IBM J. Res. Dev.,46(2/3),213–222,2002.Google Scholar
  43. 43.
    B. Davari,“CMOS technology scaling,0.1μm and beyond,”IEEE IEDM Tech. Dig.,555–558,1996.Google Scholar
  44. 44.
    L. D. Yau,“A simple theory to predict the threshold voltage of short-channel IGFETs,”Solid-State Electron.,17(10),1059–1063,1974.Google Scholar
  45. 45.
    G. W. Taylor,“The effects of two-dimensional charge sharing on the above-threshold characteristics of short-channel IGFETs,”Solid-State Electron.,25(8),22(8),701–717,1979.Google Scholar
  46. 46.
    O. Jaentsch,“A geometrical model of the threshold voltage of short and narrow-channel MOSFETs,”Solid-State Electron.,25(1),59–61,1982.Google Scholar
  47. 47.
    G. Merckel,“A simple model of the threshold voltage of short and narrow channel MOS-FETs,”Solid-State Electron.,23(12),1207–1213,1980.Google Scholar
  48. 48.
    R. R. Troutman,“VLSI limitations from drain-induced barrier lowering,”IEEE Trans. Electron,Device,ED-26(4),461–469,1979.Google Scholar
  49. 49.
    T. H. Nguyen and J. D.,Plummer,“Physical mechanisms responsible for short channel effects in MOS devices,”IEEE IEDM Tech. Dig.,596–599,1981.Google Scholar
  50. 50.
    C.-Y. Wu and S.-Y. Yang,“An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI,”Solid-State Electron.,27(7),651–658,1984.Google Scholar
  51. 51.
    S. C. Jain and P. Balk,“A unified analytical model for drain-induced barrier lowering and drain-induced high electric field in a short-channel MOSFET,”Solid-State Electron.,30(5),503–511,1987.Google Scholar
  52. 52.
    P. E. Cottrell and E. M. Buturla,“Steady state analysis of field effect transistors via the finite element method,”IEEE IEDM Tech. Dig.,51–54,1975.Google Scholar
  53. 53.
    S. Selberherr,“MINIMOS – A two-dimensional MOS transistor analyzer,”IEEE Trans. Electron Dev.,ED-27(8),1440–1560,1980.Google Scholar
  54. 54.
    J. A. Greenfield and R. W. Dutton,“Nonplanar VLSI device analysis using the solution of Poisson's equation,”IEEE Trans. Electron Dev.,ED-27(8),1520–1532,1980.Google Scholar
  55. 55.
    C. L. Wilson and J. L. Blue,“Two-dimensional finite element charge-sheet model for a short-channel MOS transistor,”Solid-State Electron.,25(6),461–477,1982.Google Scholar
  56. 56.
    W. P. Noble,“Short channel effects in dual gate field effect transistors,”IEEE IEDM Tech. Digest.,483–486,1978.Google Scholar
  57. 57.
    M. T. Bohr and Y. A. El-Mansy,“Technology for advanced high-performance microprocessors,”Trans. Electron Dev.,45(3),620–625,1998.Google Scholar
  58. 58.
    M. Nishida and H. Onodera,“An anomalous increase in threshold voltages with shortening the channel lengths for deeply boron-implanted n-channel MOSFETs,”IEEE Trans. Electron Dev.,ED-28(9),1101–1103,1981.Google Scholar
  59. 59.
    M. Orlowski,C. Mazuré,and F. Lau,“Submicron short channel effects due to gate reoxida-tion induced lateral interstitial diffusion,”IEEE IEDM Tech. Digest,632–635,1987.Google Scholar
  60. 60.
    C. Mazuré and M. Orlowski,“Guidelines for reverse short-channel behavior,”IEEE Electron Dev. Lett.,10(12),556–558,1989.Google Scholar
  61. 61.
    C.-Y. Hu and J. M. Sung,“Reverse short-channel effects on threshold voltage in submicron silicide devices,”IEEE Electron Dev. Lett.,10(10),446–448,1989.Google Scholar
  62. 62.
    T. Kunikiyo,K. Mitsui,M. Fujinaga,T. Uchida,N. Kotani,and Y. Akasaka,“Numerical modeling of processes and devices for integrated circuits,”NUPAD IV workshop,May,1992.Google Scholar
  63. 63.
    C. S. Rafferty,H.-H. Vuong,S. A. Esharghi,M. D. Giles,M. R. Pinto,and S. J. Hillenius,“Explanation of reverse short channel effect by defect gradients,”IEEE IEDM Tech. Digest,311–314,1993.Google Scholar
  64. 64.
    H. Brut,A. Juge,and G. Ghbaudo,“Physical model of threshold voltage in silicon MOS transistors including reverse short channel effects,”Electron Lett.,31(5),411–412,1995.Google Scholar
  65. 65.
    K. Nishi,H. Matsuhashi,T. Ochini,K. Kasai,and T. Nishikawa,“Evidence of channel profile modification due to implantation damage studied by new method,and its implication to reverse short channel effect of nMOSFETs,”IEEE IEDM Tech. Digest,993–995,1995.Google Scholar
  66. 66.
    B. Szelag,F. Balestra,and G. Ghibaudo,“Comprehensive analysis of reverse short-channel effect in silicon MOSFETs from low-temperature operation,”IEEE Electron Dev. Lett.,19(12),511–513,1998.Google Scholar
  67. 67.
    D. Tsoulakas,C. Tsamis,D. N. Kouvatsos,P. Revva,and E. Tsoi,“Reduction in the reverse short channel effect in thick SOI MOSFETs,”IEEE Electron Dev. Lett.,18(3),90–92,1997.Google Scholar
  68. 68.
    N. D. Arora and M. S. Sharma,“Modeling the anomalous threshold voltage behavior in submicrometer MOSFETs,”IEEE Electron Dev. Lett.,13(2),92–94,1992.Google Scholar
  69. 69.
    H. Jacobs,A. v. Schwerin,D. Scharfetter,and F. Lau,“MOSFET reverse short channel effect due to silicon interstitial capture in gate oxide,”IEEE IEDM Tech. Digest,307–310,1993.Google Scholar
  70. 70.
    J. M. Sung,C. Y. Lu,M. L. Chen,and S. J. Hillenius,“Fluorine effect on boron diffusion of p+ gate devices,”IEEE IEDM Tech. Digest,447–450,1989.Google Scholar
  71. 71.
    J. R. Pfiester,L. C. Parrillo,and F. K. Baker,“A physical model for boron penetration through thin gate oxides from p+ polysilicon gates,”IEEE Electron Dev. Lett.,11(6),247–249,1990.Google Scholar
  72. 72.
    C.-Y. Chang,C.-Y. Lin,J. W. Chou,C. C.-H. Hsu,H.-T. Pan,and J. Ko,“Anomalous reverse short-channel effect in p+ polysilicon gated p-channel MOSFET,”IEEE Electron Dev. Lett.,15(11),437–439,1994.Google Scholar
  73. 73.
    T. Hori and K. Kurimoto,“A new half-micron p-channel MOSFET with LATIPS(Large-Tilt-Angle-Implanted-Punchthrough-Stopper),”IEEE IEDM Tech. Digest,394–397,1988.Google Scholar
  74. 74.
    H. Wakabayashi,M. Ueki,M. Narihiro,T. Fukai,N. Ikezawa,T. Matsuda,K. Yishida,K. Takeuchi,Y. Ochiai,T. Mogami,and T. Kunio,“Sub-50-nm physical gate length CMOS technology and beyond using steep halo,”IEEE IEDM Tech. Digest,89–93,2002.Google Scholar
  75. 75.
    R. Qwoziecki,T. Skotnicki,P. Bouillon,and P. Gentil,“Optimization of Vth roll-off in MOS-FETs with advanced channel architecture – Retrograde doping pockets,”IEEE Trans. Electron Dev.,46(7),1551–1561,1999.Google Scholar
  76. 76.
    A. Sadovnikov,A. Kalnitsky,A. Bergemont,and P. Hopper,“The effect of polysilicon doping on the reverse short-channel effect in sub-quarter micron NMOS transistors,”IEEE Trans. Electron Dev.,48(2),393–395,2001.Google Scholar
  77. 77.
    P. P. Wang,“Device characteristics of short-channel and narrow-width MOSFETs,”IEEE Trans. Electron Dev.,ED-25(7),779–786,1978.Google Scholar
  78. 78.
    K. O. Jeppson,“Influence of the channel width on the threshold voltage modulation in m.o.s.f.e.t.s,”Electron. Lett.,11(14),997–299,1975.Google Scholar
  79. 79.
    H. N. Kotecha and K. E. Beilstein,“Current and capacitances in narrow width MOSFET structures,”IEEE IEDM Tech. Digest,47–50,1975.Google Scholar
  80. 80.
    J. D. Sansbury,“MOS field threshold increase by phosphorus-implanted field”,IEEE Trans. Electron Dev.,ED-20(5),473–476,1973.Google Scholar
  81. 81.
    M. B. Bandali and T. C. Lo,“On the modeling of the self-aligned field implanted MOS devices with narrow width,”IEEE IEDM Tech. Digest,573–576,1975.Google Scholar
  82. 82.
    H. Kotecha and W. P. Noble,“Interaction of IGFET field design with narrow channel device operation,”IEEE IEDM Tech. Digest,724–727,1980.Google Scholar
  83. 83.
    L. A. Akers,M. M. E. Beguwala,and F. Z. Custode,“A model of a narrow-width MOSFET including tapered oxide and doping encroachment,”IEEE Trans. Electron Dev.,ED-28(12),1490–1495,1981.Google Scholar
  84. 84.
    K. E. Kroell and G. K. Ackermann,“Threshold voltage of narrow channel field effect transistors,”Solid-State Electron.,19(1),77–81,1976.Google Scholar
  85. 85.
    W. P. Noble and P. E. Cottrell,“Narrow channel effects in insulated gate field effect transistors,”IEEE IEDM Tech. Digest,582–586,1976.Google Scholar
  86. 86.
    C.-R. Ji and C. T. Sah,“Analysis of the narrow gate effect in submicrometer MOSFETs,”IEEE Trans. Electron Dev.,ED-30(12),1672–1677,1983.Google Scholar
  87. 87.
    N. Shigyo,M. Konaka,R. L. M. Dang,“Three-dimensional simulation of inverse narrow-channel effect,”Electron. Lett.,18(6),274–275,1982.Google Scholar
  88. 88.
    N. Shigyo,S. Fukuda,T. Wada,K. Hieda,T. Hamamoto,H. Watanabe,K. Sunouch,and H. Tango,“Three-dimensional analysis of subthreshold swing and transconductance for fully recessed oxide(trench) isolated ¼-μm-width MOSFETs,”IEEE Trans. Electron Dev.,35(7) 945–950,1988.Google Scholar
  89. 89.
    L. A. Akers,“The inverse-narrow-width effect,”IEEE Electron Dev. Lett.,EDL-7(7),419–421,1986.Google Scholar
  90. 90.
    S. S.-S. Chung and T.-C. Li,“An analytical threshold-voltage model of trench-isolated MOS devices with nonuniformly doped substrates,”IEEE Trans. Electron Dev.,39(3),614–622,1992.Google Scholar
  91. 91.
    K. Ohe,Y. S. Kugo,H. Umimoto,and S. Odanaka,“The inverse-narrow-width effect of LOCOS isolated n-MOSFET in a high-concentration p-well,”IEEE Electron Dev. Lett.,13(12),636–638,1992.Google Scholar
  92. 92.
    E. Herbert,K. M. Hong,Y. C. Cheng,and K. Y. Chan,“The narrow-channel effect in MOSFETs with semi-recessed oxide structures,”IEEE Trans. Electron Dev.,37(3),692–670,1990.Google Scholar
  93. 93.
    L. A. Akers,M. Sugino,and J. M. Ford,“Characterization of the inverse-narrow-width effect,”IEEE Trans. Electron Dev. ED-34(12),2476–2484,1987.Google Scholar
  94. 94.
    T. Osishi,K. Shiozawa,A. Furukawa,Y. Abe,and Y. Tokuda,“Isolation edge effect depending on gate length of MOSFETs with various isolation structures,”IEEE trans. Electron Dev.,47(4),822–827,2000.Google Scholar
  95. 95.
    A. H. Parera,J.-H. Lin,Y.-C. Ku,M. Azrak,B. Taylor,J. Hayden,M. Thompson,and M. Blackwell,“Trench isolation for 0.45μm active pitch and below,”IEEE. IEDM Tech. Digest,679–682,1995.Google Scholar
  96. 96.
    S. Masuda,T. Sato,H. Yoshimura,A.Sudo,I. Mizushima,Y. Tsunashima,and Y. Toyoshima,“Novel corner rounding process for shallow-trench isolation utilizing MSTS(Micro-Structure Transformation of Silicon),”IEEE IEDM Tech. Digest,137–140,1998.Google Scholar
  97. 97.
    J. B. Kuo,Y. G. Chen,and K. W. Su,“Sidewall-related narrow-channel effect in mesa-isolated fully-depleted ultra-thin SOI NMOS devices,”IEEE Electron Dev. Lett.,16(9),379–381,1995.Google Scholar
  98. 98.
    B. Agrawal,V. K. De,and J. D. Meindl,“Three-dimensional analytical subthreshold models for bulk MOSFETs,”IEEE Trans. Electron Dev.,42(12),2170–2180,1995.Google Scholar
  99. 99.
    K. Ohe,S. Odanaka,K. Moriyama,T. Hori,and G. Fuse,“Narrow-width effects of shallow trench-isolated CMOS with n+-polysilicon gate,”IEEE Trans. Electron Eev.,36(6),1110–1116,1989.Google Scholar
  100. 100.
    A. Ono,R. Ueno,and I. Sakai,“TED control technology for suppression of reverse narrow channel effect in 0.1μm MOS devices,”IEEE IEDM Tech. Digest,227–230,1997.Google Scholar
  101. 101.
    C.-Y. Chang,S.-J. Chang,T.-S. Chao,S.-D. Wu,and T.-Y. Huang,“Reduced reverse narrow channel effect in thin SOI nMOSFETs,”IEEE Electron Dev. Lett.,21(9),460–462,2000.Google Scholar
  102. 102.
    S.-J. Chang,C.-Y. Chang,C. Chen,J.-Y. Chou,T.-S. Chao,and T.-Y. Huang,“An anomalous crossover in Vth toll-off for indium-doped nMOSFETs,”IEEE Electron Dev. Lett.,21(9),457–459,2000.Google Scholar
  103. 103.
    J. Kim,T. Kim,J. Park,W. Kim,B. Hong,and G. Yoon,“A shallow trench isolation using nitric oxide(NO)-annealed wall oxide to suppress inverse narrow width effect,”IEEE Electron Dev. Lett.,21(12),575–577,2000.Google Scholar
  104. 104.
    C. P. Chang,C. S. Pai,F. H. Baumann,C. T. Liu,C. S. Rafferty,M. R. Pinto,E. J. Lloyd,M. Bude,F. P. Klemens,J. F. Miner,K. P. Cheung,J. I. Colonell,W. Y. C. Lai,H. Vaidya,S. J. Hillenius,R. C. Liu,and J. T. Clemens,“A highly manufacturable corner rounding solution for 0.18μm shallow trench isolation,”IEEE IEDM Tech. Digest,661–664,1997.Google Scholar
  105. 105.
    T. Sato,I. Mizushima,J.-I. Iba,M. Kito,Y. Takegawa,A. Sudo,and Y. Tsunashima,“Trench transformation technology using hydrogen annealing for realizing highly reliable device structure with thin dielectric film,”VLSI Tech. Digest,206–207,1998.Google Scholar
  106. 106.
    K. Horita,T. Kuroi,Y. Itoh,K. Shiozawa,K. Eikyu,K. Goto,Y. Inoue,and M. Inuishi,“Advanced shallow trench isolation to suppress the inverse narrow channel effects for 0.24μm pitch isolation and beyond,”VLSI Tech. Digest,179–180,2000.Google Scholar
  107. 107.
    W. P. Noble,A. K. Ghatalia,and B. El-Kareh,“MOSFET with raised STI isolation self-aligned to the gate stack,”US patent 5,539,229,Dec. 28,1994.Google Scholar
  108. 108.
    J.-W. Lee,Y. Saitoh,R. Koh,and T. Mogami,“Elevated field insulator(ELFIN) process for device isolation of ultrathin SOI MOSFETs with top silicon film less than 20 nm,”IEEE Electron Dev. Lett.,32(8),467–469,2002.Google Scholar
  109. 109.
    C. T. Liu,F. H. Baumann,A. Ghetti,H. H. Vuong,C. P. Chang,K. P. Cheung,J. I. Colonell,W. Y. C. Lai,E. J. Lloyd,J. F. Miner,C. S. Pai,H. Vaidya,R. C. Liu,and J. T. Clemens,“Severe thickness variation of sub-3 nm gate oxide due to Si surface faceting,poly-Si intrusion,and corner stress,”VLSI Tech. Digest,94–95,1999.Google Scholar
  110. 110.
    M. Togo,K. Watanabe,M. Terai,T. Fukai,M. Narihiro,K. Arai,S. Koyama,N. Ikezawa,T. Tatsumi,and T. Mogami,“Impact of radical oxynitridation on characteristics and reliability of sub-1.5 nm-thick gate dielectric FETs with narrow channel and shallow-trench isolation,”IEEE IEDM Tech. Digest,813–816,2001.Google Scholar
  111. 111.
    M. Togo,K. Watanabe,M. Terai,T. Yamamoto,T. Fukai,T. Tatsumi,and T. Mogami,“Improving the quality of sub-1.5-nm-thick oxynitride gate dielectric for FETs with narrow channel and shallow-trench isolation using radical oxygen and nitrogen,”IEEE Trans. Electron Dev.,49(10),1736–1741,2002.Google Scholar
  112. 112.
    K. H.-L. Hsueh,J. J. Sanchez,T. A. Demassa,and L. A. Akers,“Inverse-narrow-width and small-geometry MOSFET threshold voltage model,”IEEE Trans. Electron Dev.,35(3),325–338,1988.Google Scholar
  113. 113.
    B. Hoeneisen and C. A. Mead,“Fundamental limitations in microelectronics – I. MOS technology,”Solid-State Electron.,15(7),819–829,1972.Google Scholar
  114. 114.
    R. W. Keyes,“Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics,”IEEE J. Solid-State Circuits,10(4),245–247,1975.Google Scholar
  115. 115.
    T. Mizuno,J.-I. Okamura,and A. Toriumi,“Experimental study of threshold voltage fluctuations due to statistical variation of channel dopant number in MOSFETs,”IEEE Trans. Electron Dev.,41(11),2216–2221,1994.Google Scholar
  116. 116.
    P. A. Stolk and D. B. M. Klaassen,“The effect of statistical dopant fluctuation on MOS device performance,”IEEE IEDM,Tech. Digest,627–630,1996.Google Scholar
  117. 117.
    P. A. Stolk,F. P. Widdershoven,and D. B. M. Klaassen,“Modeling statistical dopant fluctuations in MOS transistors,”IEEE Trans. Electron Dev.,45(5),1960–1971,1998.Google Scholar
  118. 118.
    H.-S. Wong and Y. Taur,“Three-dimensional ‘atomistic’ simulation of discrete random dopant distribution effect in sub-0.1μm MOSFETs,”IEEE IEDM,Tech. Digest,705–708,1993.Google Scholar
  119. 119.
    K. R. Lakshimikumar,R. A. Hadaway,and M. A. Copeland,“Characterization and modeling of mismatch in MOS transistors for precision analog design,”IEEE J. Solid-State Circuits,21(12),1057–1066,1986.Google Scholar
  120. 120.
    M. J. M Pelgrom,A. C. J. Duinmaijer,and A. P. G. Welbers,“Matching properties of MOS transistors,”IEEE J. Solid-State Circuits,24(10),1433–1440,1989.Google Scholar
  121. 121.
    P. G. Drennan and C. C. McAndrew,“A comprehensive MOSFET mismatch model,”IEDM Tech. Digest,167–170,1989.Google Scholar
  122. 122.
    H. Yang,V. Macary,J. L. Huber,W.-G Min,B. Baird,and J. Zuo,“Current Mismatch due to local dopant fluctuations in MOSFET channel,”IEEE Trans. Electron Dev.,50(11),2248–2254,2003.Google Scholar
  123. 123.
    S.-C. Liu,J. B. Kuo,K.-T. Huang,and S.-W. Sun,“A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation,”,IEEE Trans. Electron Dev.,47(4),725–733,2000.Google Scholar
  124. 124.
    S. K. Tewksbury,“N-channel enhancement-mode MOSFET characteristics from 10 to 300 K,”IEEE Trans. Electron Dev.,ED-28(12),1519–1529,1981.Google Scholar
  125. 125.
    M. Aoki,T. Ishii,T. Yoshimura,Y. Kiyota,S. Iijima,T. Yamanaka,T. Kure,K. Ohyu,T. Nishida,S. Okazaki,K. Seki,and K. Shimohigashi,“0.1μm CMOS devices using low-impurity channel transistors(LICT),”IEEE IEDM,Tech. Digest,939–941,1990.Google Scholar
  126. 126.
    K. Noda,T. Tatsumi,T. Uchida,K. Nakajima,H. Miyamoto,and C. Hu,“A 0.1-μm delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy,”IEEE Trans. Electron Dev.,45(4),809–814,1998.Google Scholar
  127. 127.
    A. Hori,T. Hirai,M. Tanaka,H. Nakaoka,H. Umimoto,and M. Yasuhira,“A 0.1-μm CMOS with a step channel profile formed by ultra high vacuum CVD and in-situ doped ions,”IEEE IEDM Tech. Digest,909–911,1993.Google Scholar
  128. 128.
    A. Asenov and S. Saini,“Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-μm MOSFETs with epitaxial and d-doped channels,”IEEE trans. Electron Dev.,46(8),1718–1724,1999.Google Scholar
  129. 129.
    R.-H. Yan,A. Ourmazd,and K. F. Lee,“Scaling of Si MOSFET: from bulk to SOI to bulk,”IEEE Trans. Electron Dev.,39(7),1704–1710,1992.Google Scholar
  130. 130.
    K. F. Lee,R. H. Yan,D. Y. Jeon,G. M. Chin,Y. O. Kim,D. M. Tennant,B. Razavi,H. D. Lin,Y. G. Wey,E. H. Westerwick,M. D. Morris,R. W. Johnson,T. M. Liu,M. Tarsia,M. Cerullo,R. G. Swartz,and A. Ourmazd,Room temperature 0.1μm CMOS technology with 11.8 ps gate delay,”IEEE IEDM Tech. Digest,131–133,1993.Google Scholar
  131. 131.
    N. Kawakami,K. Egusa,and K. Shibahara,“Reduction of threshold voltage fluctuation of p-MOSFETs by antimony super steep retrograde well channel,”Second International Workshop on Junction Technology,7–10,2001.Google Scholar
  132. 132.
    J. B. Jacobs and D. Antoniadis,“Channel profile engineering for MOSFETs with 100 nm channel length,”IEEE Trans. Electron Dev.,42(5),870–875,1995.Google Scholar
  133. 133.
    J.-H. Lee,J. Lee,S. Talwar,Y. Wang,D. Weon,S. Hahn,C. Kang,T. Hong,Y. Kim,H. Lee,S. Lee,J. Rob,D. Kang,and J. Park,“Laser thermal annealed SWSR well prior to epi-channel growth(LASPE) for 70 nm nFETs,”IEEE IEDM Tech. Digest,441–444,2000.Google Scholar
  134. 134.
    S. Venkatesan,J. W. Lutze,C. Lage,and W. J. Taylor,“Device drive current degradation observed with retrograde channel profiles,”IEEE IEDM Tech. Digest,419–422,1995.Google Scholar
  135. 135.
    S. E. Thompson,P. A. Packan,and M. T. Bohr,“Linear versus saturated drive current: tradeoffs in super steep retrograde well engineering,”VLSI Tech. Digest,154–255,1996.Google Scholar
  136. 136.
    J. G. Ruch,“Electron dynamics in short channel field-effect transistors,”IEEE Trans. Electron Dev.,ED-19(5),652–654,1972.Google Scholar
  137. 137.
    D. K. Ferry,J. R. Barker,and H. L. Grubin,“Hot-carrier constraints on transient transport in very small semiconductor devices,”IEEE Trans. Electron Dev.,ED-38(8),905–911,1981.Google Scholar
  138. 138.
    Y.-J. Park,T.-W. Tang,and D. H. Navon,“Monte Carlo surface scattering simulation in MOSFET structures,”IEEE Trans. Electron Dev.,30(9),1110–1116,1983.Google Scholar
  139. 139.
    S. E. Laux and M. V. Fischetti,“Monte Carlo simulation of submicrometer Si n-MOSFETs at 77 and 300 K,”IEEE Electron Dev. Lett.,9(9),467–469,1988.Google Scholar
  140. 140.
    G. Baccarani and M. R. Wordeman,“An investigation of steady-state velocity overshoot in silicon,”Solid-State Electron.,28(4),407–416,1985.Google Scholar
  141. 141.
    T. Kobayashi and K. Saito,“Two-dimensional analysis of velocity overshoot effects in ultrashort-channel Si MOSFETs,”IEEE Trans. Electron Dev.,ED-33(4),788–792,1985.Google Scholar
  142. 142.
    G. A. Sai-Halasz,M. R. Wordemann,D. P. Kern,S. Rischton,and E. Ganin,“High transcon-ductance and velocity overshoot in NMOS devices at the 0.1-μm gate-length level,”IEEE Electron Dev. Lett.,9(9),464–466,1988.Google Scholar
  143. 143.
    S. Y. Chou,D. A. Antoniadis,and H. I. Smith,“Observation of electron velocity overshoot in sub-100-nm-channel MOSFETs in silicon,”IEEE Electron Dev. Lett.,6(12),665–667,1985.Google Scholar
  144. 144.
    T. Sato,Y. Takeishi,and H. Hara,“Mobility anisotropy of electrons in inversion layers on oxidized silicon surfaces,”Phys. Rev. B.,4(6),1950–1960,1971.Google Scholar
  145. 145.
    C. T. Sah,J. R. Edwards,and T. H. Ning,“Observation of mobility anisotropy of electrons on(110) silicon surfaces at low temperatures,”Physica Status Solidi(a),10(1),153–160,1972.Google Scholar
  146. 146.
    S.-i. Tagaki,A. Toriumi,M. Iwase,and H. Tango,“On the universality of inversion layer mobility in Si MOSFETs: Part II – effects of surface orientation,”IEEE Trans. Electron Dev.,41(12),2362–2368,1994.Google Scholar
  147. 147.
    D. Colman,R. T. Bate,and J. P. Mize,“Mobility anisotropy and piezoresistance in silicon p-type inversion layers,”J. Appl. Phys.,39(4) 1823–1831,1968.Google Scholar
  148. 148.
    H. Sayama,Y. Nishida,H. Oda,T. Oishi,S. Shimizu,T. Kunikiyo,S. Sonoda,Y. Inoue,and M. Inuishi,”Effect of <100> channel direction for high performance SCE immune pMOSFET with less than 0.15μm gate length,”IEEE IEDM Tech. Digest,657–660,1999.Google Scholar
  149. 149.
    M. Yang,V. W. C. Chan,K. K. Chan,L. Shi,D. M. Fried,J. H. Sathis,A. I. Chou,E. P. Gusev,J. A. Ott,L. E. Burns,M. V. Fischetti,and M. Ieong,“Hybrid-orientation technology(HOT): Opportunities and challenges,”IEEE Trans. Electron Dev.,53(5),965–978,2006.Google Scholar
  150. 150.
    M. Yang,E. P. Gusev,M. Ieong,O. Gluschnkov,D. C. Boyd,K. K. Chan,P. M. Kozlowski,C. P. D'Emic,R. M. Sicina,P. C. Jamison,and A. I. Chou,“Performance dependence of CMOS silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics,”IEEE Electron Dev. Lett.,24(5),339–341,2003.Google Scholar
  151. 151.
    H. S. Momose,T. Ohguro,K. Kojima,S.-I. Nakamura,and Y. Toyoshima,“1.5-nm gate oxide CMOS on(100) surface-oriented Si substrate,”IEEE Trans. Electron Dev.,50(4),1001–1007,2003.Google Scholar
  152. 152.
    M. Kinugawa,M. Kakumu,T. Usami,and J. Matsugana,“Effects of silicon surface orientation on submicron CMOS devices,”IEEE IEDM Tech. Digest,581–584,1985.Google Scholar
  153. 153.
    T. Mizuno,N. Sugiyama,T. Tezuka,Y. Moriyama,S. Nakaharai,T. Maeda,and S. Takagi,“Physical mechanism for high hole mobility in(110)-surface strained- and unstrained-MOSFETs,”IEEE IEDM Tech. Digest,809–812,2003.Google Scholar
  154. 154.
    K. Onishi,C. S. Kang,R. Choi,H.-J. Cho,Y. H. Kim,S. Krishnan,M. S. Akbar,and J. C. Lee,“Performance of polysilicon gate HfO2 MOSFETs on(100) and(111) silicon substrate,”IEEE Electron Dev. Lett.,24(4) 254–256,2003.Google Scholar
  155. 155.
    L. Chang,M. Ieong,and M. Yang,“CMOS circuit performance enhancement by surface orientation optimization,”IEEE Trans. Electron Dev.,51(10),1621–1627,2004.Google Scholar
  156. 156.
    H. Nakamura,T. Ezaki,T. Ewamoto,M. Togo,T. Ikezawa,N. Ikarashi,M. Hane,and T. Yamamoto,“Effects of selecting channel direction in improving performance of sub-100 nm MOSFETs fabricated on(110) surface Si substrate,”Jap. J. Appl. Phys.,43(4B),1723–1728,2004.Google Scholar
  157. 157.
    M. Aoki,K. Yano,T. Masuhara,and K. Shimohigashi,“Fully symmetric cooled CMOS on(110) plane,”IEEE Trans. Electron Dev.,36(8),1429–1433,1989.Google Scholar
  158. 158.
    M. J. van Dort,P. H. Woerlee,A. J. Walker,C. A. H. Juffermans,and H. Lifka,“Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFETs,”IEEE Trans. Electron Dev.,39(4),932–938,1992.Google Scholar
  159. 159.
    S. Tagaki,M. Iwase,and A. Toriumi,“On the universality of inversion-layer mobility,”IEEE IEDM Tech. Digest,398–401,1988.Google Scholar
  160. 160.
    A. Hiroki,S. Odanaka,K. Ohe,and H. Esaki,“A mobility model for submicrometer MOS-FET simulations including hot-carrier-induced device degradation,IEEE Trans. Electron Dev.,35(9),1487–1493,1988.Google Scholar
  161. 161.
    F. Gamiz,J. B. Roldan,H. Kosina,and T. Grasser,“Improving strained-Si on Si1-xGex deep submicron MOSFETs performance by means of stepped doping profile,”IEEE Trans. Electron Dev.,48(9),1878–1884,2001.Google Scholar
  162. 162.
    W. P. Soppa and H.-G. Wagemann,“Investigation and modeling of the surface mobility of MOSFETs from −25 to +150°C,”IEEE Trans. Electron Dev.,35(7),970–977,1988.Google Scholar
  163. 163.
    D. K. Ferry,“Effects of surface roughness in inversion layer transport,”IEEE IEDM Tech. Digest,605–608,1984.Google Scholar
  164. 164.
    Y. C. Cheng and E. A. Sullivan,“On the role of scattering by surface roughness in silicon inversion layers,”Surface Science,34(3),717–731,1973.Google Scholar
  165. 165.
    K. Sonoda,K. Taniguchi,and C. Himaguchi,“Analytical device model for submicrometer MOSFETs,”IEEE Trans. Electron Dev.,38(12),2662–2668,1991.Google Scholar
  166. 166.
    C. S. Smith,“Piezoresistance effect in germanium and silicon,”Phys. Rev. B.,94(1),42–46,1954.Google Scholar
  167. 167.
    R. W. Keyes,“High-mobility FET ins strained silicon,”IEEE Trans. Electron Dev.,ED-33(6),853,1986.Google Scholar
  168. 168.
    J. Wesler,J. L. Hoyt,S. Takagi,and J. F. Gibbons,“Strain dependence of the performance enhancement in strained-Si-n-MOSFETs,”IEEE IEDM Tech. Digest,373–376,1994.Google Scholar
  169. 169.
    K. Rim,J. L. Hoyt,and J. F. Gibbons,“Fabrication and analysis of deep submicron strained-Si N-MOSFETs,”IEEE Trans. Electron Dev.,47(7),1406–1415,2000.Google Scholar
  170. 170.
    K. Rim,S. Koester,M. Hatgrove,J. Chu,P. M. Mooney,J. Ott,T. Kanarsky,P. Ronsheim,M. Ieong,A. Grill,and H.-S. P. Wong,“Strained Si NMOSFETs for high-performance CMOS technology,”VLSI Tech. Digest,50–51,2001.Google Scholar
  171. 171.
    H. M. Nayfey,C. W. Leitz,A. J. Pitera,E. A. Fitzgerald,J. L. Hoyt,and D. A. Antoniadis,“Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs,”IEEE Electron Device Lett.,24(4),248–250,2003.Google Scholar
  172. 172.
    C.-H. Ge,C.-C. Lin,C.-H. Ko,C.-C. Huang,B.-W. Chan,B.-C. Perng,V.-C. Sheu,P.-Y. Tsai,L.-G. Yao,C.-L. Wu,T.-L. Lee,C.-J. Chen,C.-T. Wang,S.-C. Lin,Y.-C. Yeo,and C. Hu,“Process-strained Si(PSS) CMOS technology featuring 3D strain engineering,”IEEE IEDM Tech. Digest,73–76,2003.Google Scholar
  173. 173.
    S. E. Thompson,M. Armstrong,C. Auth,M. Alavi,M. Buchler,R. Chau,S. Cea,T. Ghani,T. Hoffman,C.-H. Jan,C. Kenyon,J. Klaus,K. Kuhn,Z. Ma,B. Mcintyire,K. Mistry, A. Murthy,B. Obradovic,R. Nagisetty,P. Nguyen,S. Sivakumar,R. Shaheed,L.. Shifren, B. Tufts,S. Tyagi,M. Bohr,and Y. El-Masry,“A 90-nm logic technology featuring strained-silicon,”IEEE Trans. Electron Dev.,51(11),1790–1796,2004.Google Scholar
  174. 174.
    M. L. Lee and E. A. Fitzgerald,“Hole mobility enhancements in nanometer-scale strained-silicon heterostructures grown on Ge-rich relaxed Si1−xGex,”J. Appl. Phys.,94(4),2590–2596,2003.Google Scholar
  175. 175.
    K. Ishimaru,M. Takayanagi,T. Watanabe,S. Inaba,M. Fujiwara,and D. Matsushita,“Scaled CMOS with SiON and high-k,”209th ECS Meeting,Silicon Materials Science and Technology,Denver,Colorado,2006.Google Scholar
  176. 176.
    B. Brar,G. D. Wilk,and A. C. Seabaugh,“Direct extraction of the electron tunneling effective mass in ultrathin SiO2,”Appl. Phys. Lett.,69(18),2728–2730,1996.Google Scholar
  177. 177.
    G. D. Wilk,R. M. Wallace,and J. M. Anthony,“High-k gate dielectrics: Current status and material properties considerations,”Appl. Phys. Rev.,89(10),5243–5275,2001.Google Scholar
  178. 178.
    T. M. Pan,T. F. Lei,H. C. Wen,and T. S. Chao,“Characterization of ultrathin oxynitride(18–21 Å) gate dielectrics by NH3 nitridation and N2O RTA treatment,”IEEE Trans. Electron Dev.,48(5),907–912,2001.Google Scholar
  179. 179.
    T. M. Pan,T. F. Lei,and T. S. Chao,“Robust ultrathin oxynitride dielectrics by NH3 nitrida-tion and N2O RTA treatment,”IEEE Electron Dev. Lett.,21(8),178–180,2000.Google Scholar
  180. 180.
    S. C. Song,H. F. Luan,Y. Y. Chen,M. Gardner,J. Fulford,M. Allen,and D. L. Kwong,“Ultra Thin(<20Å) CVD Si3N4 gate dielectric for deep-sub-micron CMOS devices,”IEEE IEDM Tech. Digest,373–376,1998.Google Scholar
  181. 181.
    T. P. Ma,“Making silicon nitride film a viable gate dielectric,”IEEE Trans. Electron Dev.,45(3),680–690,1998.Google Scholar
  182. 182.
    S. C. Song,H. F. Luan,C. H. Lee,A. Y. Mao,S. J. Lee,J. Gelpey,S,Marcus,and D. L. Kwong,“Ultra thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N2O oxidation of NH3-nitrided Si,”Digest VLSI Technol. Syst. Applic.,78–81,1999.Google Scholar
  183. 183.
    V. J. Kapoor,R. S. Bailey,and H. J. Stein,“Hydrogen-related memory traps in thin silicon nitride films,”J. Vac. Sci. Technol.,A,1(2),600–603,1983.Google Scholar
  184. 184.
    K. Allaert,A,Van Calster,H. Loos,and A. Lequesne,“A comparison between silicon nitride films made by PCVD on N2-SiH4/Ar and N2-SiH4/He,”J. Electrochem Soc.,132(7),1763–1766,1985.Google Scholar
  185. 185.
    J. Robertson,“Band offsets of wide-band-gap oxides and implications for future electronics,”J. Vac. Sci. Technol.,B 18(3),1785–1791,2000.Google Scholar
  186. 186.
    K. J. Hubbard and D. G. Schlom,“Thermodynamic stability of binary oxides in contact with silicon,”J. Mater. Res.,11(11),2757–2761,1997.Google Scholar
  187. 187.
    C. Hobbs,T. Tseng,K. Reid,B. Taylor,L. Dip,L. Hebert,R. Garcia,R. Hegde,J. Grant,D. Gilmer,A. Franke,V. Dhandapani,M. Azrak,L. Prabhu,R. Rai,S. Bagchi,J. Conner,S. Backer,F. Dumbuya,B. Nguyen,and P. Tobin,“80 nm poly-Si gate CMOS with HfO2 gate dielectric,”IEEE IEDM Tech. Digest,651–654,2001.Google Scholar
  188. 188.
    X. Yu,M. Yu,and C. Zhu,“A comparative study of HfTaON/SiO2 and HfON/SiO2 gate stacks with TaN metal gate for advanced CMOS applications,”IEEE Trans. Electron Dev.,54(2),284–290,2007.Google Scholar
  189. 189.
    A. L. P. Rotondaro,M. R. Visokay,J. J. Chambers,A. Shanware,R. Khamankar,H. Bu,R. T. Laaksonen,L. Tsung,M. Douglas,R. Kuan,M. J. Bevan,T. Grider,J. McPherson,and L. Colombo,“Advanced CMOS Transistors with a Novel HfSiON Gate Dielectric,”VLSI Tech. Digest,148–149,2002.Google Scholar
  190. 190.
    T. Yamaguchi,R. Iijima,T. Ino,A. Nishiyama,H. Satake,and N. Fukushima,“Additional scattering effects for mobility degradation in Hf-silicate gate MISFETs,”IEEE IEDM Tech. Digest,621–624,2002.Google Scholar
  191. 191.
    Z. Ren,M. V. Fischetti,E. P. Geusev,E. A. Cartier,and M. Chudzik,“Inversion channel mobility in high-k high performance MOSFETs,”IEDM Tech. Digest,793–796,2003.Google Scholar
  192. 192.
    A. Morioka,H. Watanabe,M. Miyamura,T. Tatsumi,M. Saitoh,T. Ogura,T. Iwamoto,T. Ikarashi,Y. Saito,Y. Okada,H. Watanabe,Y. Mochiduki,and T. Mogami,“High mobility MISFET with low trapped charge in HfSiO films,”VLSI. Tech. Digest,165–166,2003.Google Scholar
  193. 193.
    A. Chin,C. C. Liao,C. H. Lu,W. J. Chen,and C. Tsai,“Device and reliability of high-K Al2O3 gate dielectric with good mobility and low Dit,”VLSI. Tech. Digest,135–136,1999.Google Scholar
  194. 194.
    A. Chin,Y. H. Wu,S. B. Chen,C. C. Liao,and W. J. Chen,“High-quality La2O3 and Al2O3 gate dielectrics with equivalent oxide thickness 5–10 Å,”VLSI. Tech. Digest,16–17,2000.Google Scholar
  195. 195.
    D. A. Buchanan,E. P. Gusev,E. Cartier,H. Okorn-Schymidt,K. Rim,M. A. Gribelyuk,A. Mokuta,A. Ajmera,M. Copel,S. Guha,N. Bojarczuk,A. Callegari,C. D'Emic,P. Kozlowski,K. Chan,R. J. Fleming,P. C. Jamison,J. Brown,and R. Arndt,“80-nm poly-silicon gated n-FETs with ultra-thin Al2O3 gate dielectric for ULSI applications,”IEEE IEDM Tech. Digest,223–226,2000.Google Scholar
  196. 196.
    S.-J. Ding,H. Hu,C. Zhu,M. F. Li,S. J. Kim,B. J. Cho,D. S. H. Chan,M. B. Yu,A. Y. Du,A. Chin,and D.-L. Kwong,“Evidence and understanding of ALD HfO2-Al2O3 laminate MIM capacitors outperforming sandwich counterparts,”IEEE Electron Dev. Lett.,25(10),681–683,2004.Google Scholar
  197. 197.
    C. Kizilyalli,R. Y. S. Huang,and P. K. Roy,“MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration of CMOS technologies,”IEEE Trans. Electron Dev.,19(11),423–425,1998.Google Scholar
  198. 198.
    B. C. Lai,J.-C. Yu,and J. Y.-M. Lee,“Ta2O5/silicon barrier height measured from nMOSFETs fabricated with Ta2O5 gate dielectric,”IEEE Electron Dev. Lett.,22(5),221–223,2001.Google Scholar
  199. 199.
    K. W. Kwon,I. S. Park,D. H. Han,E. S. Kim,S. T. Ahn,and M. Y. Lee,“Ta2O5 capacitors for 1 Gbit DRAM and beyond,”IEDM Tech. Dig.,835–838,1994.Google Scholar
  200. 200.
    M. Hiratani,T. Hamada,S. Iijima,Y. Ohji,I. Asano,N. Nakanishi,and S. Kimura,“A het-eroepitaxial MIM-Ta2O5 capacitor with enhanced dielectric constant for DRAMs of G-bit generation and beyond,”VLSI Tech. Digest,41–42,2001.Google Scholar
  201. 201.
    A. Nitayama,Y. Kohyama,and K. Hieda,“Future directions for DRAM memory cell technology,”IEEE IEDM Tech. Digest,335–338,1998.Google Scholar
  202. 202.
    B. T. Lee,K. H. Lee,C. S. Hwang,W. D. Kim,H. Horii,H.-W. Kim,H.-J. Cho,C. S. Kang,J. H. Chung,S. I. Lee,and M. Y. Lee,“Integration of(Ba,Sr)Ti03 capacitor with platinum electrodes having Si02 spacer,”IEEE IEDM Tech. Digest,249–252,1997.Google Scholar
  203. 203.
    M. Hiratani,T. Nabatame,Y. Matsui,Y. Shimamoto,Y. Sasago,Y. Nakamura,Y. Ohji,I. Asano,and S. Kimura,“A conformal ruthenium electrode for MIM capacitors in Gbit DRAMs using the CVD technology based on oxygen-controlled surface reaction,”VLSI Tech. Digest,102–103,2000.Google Scholar
  204. 204.
    H. Horii,B. T. Lee,H. J. Lim,S. H. Joo,C. S. Kang,C. Y. Yoo,H. B. Park,W. D. Kim,S. I. Lee,and M. Y. Lee,“A self-aligned stacked capacitor using novel Pt electroplating method for 1 Gbit DRAMs and beyond,”VLSI Tech. Digest,103–104,1999.Google Scholar
  205. 205.
    T.-J. King,J. R. Pfiester,J. D. Schott,J. P. McVittie,and K. C. Saraswat,“A polycrystalline-Si1−xGex-gate CMOS technology,”IEEE IEDM tech. Digest,253–256,1990.Google Scholar
  206. 206.
    T.-J. King,J. P. McVittie,K. C. Saraswat,and J. R. Pfiester,“Electrical properties of heavily doped polycrystalline silicon-germanium films,”IEEE Trans. Electron Dev.,41(2),228–232,1994.Google Scholar
  207. 207.
    Y. V. Ponomarev,P. A. Stolk,C. Salm,J. Schmitz,and P. H. Woerlee,“High-performance deep submicron CMOS technologies with polycrystalline-SiGe gates,”IEEE Trans. Electron Dev.,47(4),848–855,2000.Google Scholar
  208. 208.
    P.-E. Hellberg,S.-L. Zhang,and C. S. Petersson,“Work function of boron-doped polycrys-talline SixGe1−x films,”IEEE Electron Dev. Lett.,18(9),456–458,1997.Google Scholar
  209. 209.
    V. Z.-Q. Li,M. R. Mirabedini,R. T. Kuehn,j. J. Wortman,and C. Ozturk,“Single gate 0.15 mm CMOS devices fabricated using RTCVD in-situ boron doped Si1−xGex gates,”IEEE IEDM Tech. Digest,833–836,1997.Google Scholar
  210. 210.
    N. Kasai,N. Endo,and A. Ishitani,“Deep-submicron tungsten gate CMOS technology,”IEEE IEDM Tech. Digest,242–245,1988.Google Scholar
  211. 211.
    D. H. Lee,S. W. H. Joo,G. H. Lee,J. Moon,T. E. W. Shim,and J. G. Lee,“Characteristics of CMOSFETs with sputter-deposited W/TiN stack gate,”VLSI Tech.,119–120,1995.Google Scholar
  212. 212.
    J. C. Hu,H. Yang,R. Kraft,A. L. P. Rotondaro,S. Hattangady,W. W. Lee,R. A. Chapman,C.-P. Chao,A. Chatterjee,M. Hanratty,M. Rodder,and I.-C. Chen,“Feasibility of using W/TiN as metal gate for conventional 0.13μm CMOS technology and beyond,”IEEE IEDM Tech. Digest,825–828,1997.Google Scholar
  213. 213.
    B. Maiti,P. J. Tobin,C. Hobbs,R. I. Hegde,F. Huang,D. L. O'Meara,D. Jovanovic,M. Mendicino,J. Chen,D. Connelly,O. Adetutu,J. Mogab,J. Candelaria,and L. B. La,“PVD YiN gate NMOSFETs on bulk silicon and fully depleted silicon-on-insulator(FD-SOI) substrates for deep sub-quarter micron CMOS technology,”IEEE IEDM Tech. Digest,781–784,1998.Google Scholar
  214. 214.
    R. Li and Q. Xu,“Damascene E/TiN gate MOSFETs with improved performance for 0.1-μm regime,”IEEE Trans. Electron Dev.,49(11),1891–1896,2002.Google Scholar
  215. 215.
    J.-M. Hwang and G. Pollack,“Novel polysilicon stacked-gate structure for fully-depleted SOI/CMOS,”IEEE IEDM Tech. Digest,345–348,1992.Google Scholar
  216. 216.
    I. De,D. Johri,A. Srivastava,and C. M,Osburn,“Impact of gate workfunction on device performance at the 50 nm technology node,”Solid-State Electron.,44(8),1077–1080,2000.Google Scholar
  217. 217.
    Y. Abe,T. Oishi,K. Shiozawa,Y. Takuda,and S. Satoh,“Simulation study of comparison between metal gate and polysilicon gate for sub-quarter-micron MOSFETs,”IEEE Electron Dev. Lett.,29(12),632–634,1999.Google Scholar
  218. 218.
    E. Josse and T. Stotnicki,“Polysilicon gate with depletion – or – metallic gate with buried channel: what evil is worse?,”IEEE IEDM Tech. Digest,661–664,1999.Google Scholar
  219. 219.
    K. Maitra and V. Misra,“A simulation study to evaluate the feasibility of midgap workfunc-tion metal gates in 25 nm bulk CMOS,”IEEE Electron Dev. Lett.,24(11),707–709,2003.Google Scholar
  220. 220.
    H. Zhong,G. Heuss,and V. Misra,“Electrical properties of RuO2 gate electrodes for dual metal gate Si-CMOS,”IEEE Electron Dev. Lett.,21,(12),593–595,2000.Google Scholar
  221. 221.
    H. B. Michaelson,“The work function of the elements and its periodicity,”J. Appl. Phys.,48(11),4729–4733,1977.Google Scholar
  222. 222.
    Z. B. Zhaolin Wei,P. Grange,and B. Delmon,“XPS and XRD studies of fresh and sulfided MO2N,”Appl. Surf. Sci.,135,107–114,Sept. 1998.Google Scholar
  223. 223.
    Q. Lu,R. Lin,P. Ranade,Y. C. Yeo,X. Meng,H. Takeuchi,T.-J. King,C. Hu,H. Luan,S. Lee,W,Bai,C.-Ho. Lee,D.-L. Kwong,X. Guo,X. Wang,and T. P. Ma,“Molybdenum metal gate MOS technology for post-Si02 gate dielectrics,”IEEE IEDM Tech. Digest,641–644,2000.Google Scholar
  224. 224.
    H. Wakabayashi,Y. Saito,K. Takeuchi,T. Mogami,and T. Kunio,“A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film,”IEEE Trans. Electron Dev. 48(10),2363–2369,2001.Google Scholar
  225. 225.
    V. Misra,H. Zhong,and H. Lazar,“Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS,”IEEE Electron Dev. Lett.,23(6),354–356,2002.Google Scholar
  226. 226.
    J. H. Lee,Y.-S. Suh,H. Lazar,R. Jha,J. Gurganus,Y. Lin,and V. Mistra,“Compatibility of dual metal gate electrodes with high-K dielectrics for CMOS,”IEEE IEDM Tech. Digest,323–326,2003.Google Scholar
  227. 227.
    X. P. Wang,A. E.-J. Lim,H. Y. Yu,M.-F. Li,C. Ren,W.-Y. Loh,C.-X. Zhu,A. Chin,A. D. Trigg,Y.-C. Yeo,S. Biesemans,G.-Q. Lo,D.-L. Kwong,“Work function tunability of refractory metal nitrides by lanthanum or aluminum doping for advanced CMOS devices,”IEEE Trans. Electron Dev. 54(11),2871–2877,2007.Google Scholar
  228. 228.
    S. B. Samavedam,L. B. La,J. Smith,S. Dakshina-Murthy,E. Luckowski,J. Schaeffer,M. Zavala,R. Martin,V. Dhandapani,D. Triyoso,H. H. Tseng,P. J. Tobin,D. C. Gilmer, C. Hobbs,W. J. Taylor,J. M. Grant,R. I. Hedge,J. Mogab,C. Thomas,P. Abramowitz,M. Moosa,J. Conner,J. Jiang,V. Arunachalam,M. Sadd,B.-Y. Nguyen,and B. White,“Dual-metal gate CMOS with HfO2 gate dielectric,”IEEE IEDM Tech. Digest,433–436,2002.Google Scholar
  229. 229.
    Y. Nara,S. Inumiya,F. Ootsuka,and Y. Ohgi,“Integration of dual-metal-gate CMOS with sub-0.9-nm EOT HfSiON gate dielectrics,”3rd Intnl. Symp. On Adv. Gate Stack Tech.,Sept. 27,2006.Google Scholar
  230. 230.
    J. Kedzierski,E. Nowak,T. Kanarski,Y. Zhangt,D. Boyd,R. Carru8thers,C. Cabral,R. Amos,C. Lavoie,R. Roy,J. Newbury,E. Sullivan,J. Benedict,P. Saunders,K. Wong, D. Canapair,M. Krishnan,K.-L. Lee,B. A. Rainey,D. Fried,P. Cottrell,H.-S. P. Wong,M. Ieong,and W. Haensch,“Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,”IEEE IEDM Tech. Digest,247–250,2002.Google Scholar
  231. 231.
    J. H. Sim,H. C. Wen,J. P. Lu,and D. L. Kwong,“Dual work function metal gates using full nickel silicidation of doped poly-Si,”IEEE Electron Dev. Lett.,24(10),631–633,2003.Google Scholar
  232. 232.
    J.Kedzierski,D. Boyd,P. Sonsheim,S. Zafar,J. Newbery,J. Ott,C. Cabral Jr.,M. Ieong,and W. Haensch,“Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation(SIIS),”IEEE IEDM Tech. Digest,315–318,2003.Google Scholar
  233. 233.
    A. Veloso,T. Hoffmann,A. Lauwers,S. Brus,J.-F. de Marneffe,S. Locorotondo,C. Vrancken,T. Kauerauf,A. Shickova,B. Sijmus,H. Tigelaar,M. A. Pawlak,H. Y. Yu,C. Demeurisse,S. Kubicek,C. Kerner,T. Chiarella,O. Richard,H. Bender,M. Niwa,P. Ab-sil,M. Jurczak,S. Biesemans and J. A. Kittl,“Dual work function phase controlled Ni-FUSI CMOS(NiSi NMOS,Ni2Si or Ni31Si12 PMOS): Manufacturability,Reliability & Process Window Improvement by Sacrificial SiGe cap,”VLSI Tech. Digest,Paper 12.2,2006.Google Scholar
  234. 234.
    Y.-C. Yeo,T.-J. King,and C. Hu,“Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology,”J. Applied Phys. 92(12) 7266–7271,2002.Google Scholar
  235. 235.
    Y.-C. Yeo,P. Ranade,T.-J. King,and C. Hu,“Effects of high-? gate dielectric materials on metal and silicon gate workfunctions,”IEEE Electron Dev. Lett.,23(6),342–344,2002.Google Scholar
  236. 236.
    G. Brown and V. Misra,“Evaluation of Fermi level pinning in low,midgap and high work-function metal gate electrodes on ALD and MOCVD HfO2 under high temperature exposure,”IEEE IEDM Tech. Digest,295–298,2004.Google Scholar
  237. 237.
    S. B. Samavedam,L. B. La,P. J. Tobin,B. White,C. Hobbs,L. R. C. Fonseca,A. A. Demkov,J. Schaeffer,E. Luckowski,A. Martinez,M Raymond,D. Triyoso,D. Roan,V. Dhandapani,R. Garcia,S. G. H. Anderson,K. Moore,H. H. Tseng,C. Capasso,O. Adetutu,D. C. Gilmer,W. J. Taylor,R. Hedge,and J. Grant,“Fermi level pinning with sub-monolayer MeOx and metal gates,”IEEE IEDM Tech. Digest,307–31-,2003.Google Scholar
  238. 238.
    C. Hobbs,L. Fonseca,V. Dhandapani,S. Samavedam,B. Taylor,J. Grant,L. Dip,D. Triyoso,R. Hedge,D. Gilmer,R. Garcia,D. Roan,L. Lovejoy,R. Rai,L. Hebert,H. Tseng,B. White,and P. Tobin,“Fermi level pinning at the polySi/metal oxide interface,”VLSI Tech. Digest,9–10,2003.Google Scholar
  239. 239.
    K. Shirashi,K. Yamada,K. Torri,Y. Akasaka,K. Nakajima,M. Khono,T. Chikyo,H. Katajima,and T. Arikado,“Physics of Fermi level pining at the polySi/Hf-based high-k oxide interface,”VLSI Tech. Dig.,108–109,2004.Google Scholar
  240. 240.
    M. Koyama,Y. Kamimuta,T. Ino,A. Kaneko,S. Inumiya,K. Eguchi,M. Takayanagi,and A. Nishiyama,“Careful examination of the asymmetric Vfb shift problem for poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expense,”IEEE IEDM Tech. Digest,499–452,2004.Google Scholar
  241. 241.
    C. Hobbs,L. Fonseca,A. Knizhnik,V. Dhandapani,S. Samavedam,W. J. Taylor,J. M. Grant,L. Dip,D. H. Triyoso,R. I. Hedge,D. C. Gilmer,R. Garcia,D. Roan,M. L. Lovejoy, R. S. Rai,E. A. Hebert,H. H. Tseng,S. G. H. Anderson,B. E. White,and P. Tobin,“Fermi level pinning at the polySi/metal oxide interface – Part I,”IEEE Trans. Electron Dev.,51(6),971–977,2004.Google Scholar
  242. 242.
    ibid. Part II,978–984.Google Scholar
  243. 243.
    J. Tersoff,“Schottky barrier heights and the continuum of gap states,”Phys. Rev. Lett.,52(6),465–468,1984.Google Scholar
  244. 244.
    S. Xiong and J. Bokor,“A simulation study of gate line edge roughness effects on doping profiles of short-channel MOSFET devices,”IEEE Trans. Electron Dev.,51(2),228–232,2004.Google Scholar
  245. 245.
    J. A. Croon,G. Storms,S. Winkelmeier,I. Pollentier,M. Ercken,S. Decoutere,W. Sansen,and H. E. Maes,“Line edge roughness: characterization,modeling and impact on device behavior,”IEEE IEDM Tech. Digest,307–310,2002.Google Scholar
  246. 246.
    S. Xiong, J. Bokor, Q. Xiang, P. Fisher, I. Dudley, P. Rao, H. Wang, and B. En, “Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micron bulk MOSFET devices?,” IEEE Trans. Semicon. Manuf., 17 (3), 357–361, 2004.Google Scholar
  247. 247.
    T. Linton, M. Chandhok, B. J. Rice, and G. Schrom,“Determination of the line edge roughness specification for 34 nm devices,” IEEE IEDM Tech. Digest, 303–306, 2002.Google Scholar
  248. 248.
    C. H. Díaz, H.-J. Tao, Y.-C. Ku, A. Yen, and K. Young,“An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling,” IEEE Electron Dev. Lett., 22 (6), 287–289, 2001.Google Scholar
  249. 249.
    H.-W. Kim, J.-Y. Lee, J. Shin, S.-G. Woo, H.-K. Cho, and J.-T. Moon,“Experimental Investigation of the impact of LWR sub-100-nm device performance,” IEEE Trans. Electron Dev., 51 (12), 1984–1988, 2004.Google Scholar
  250. 250.
    H. Fukutome, Y. Momiyama, T. Kubo, Y. Tagawa, T. Aoyama, and H. Arimoto “Direct evaluation of gate line edge roughness impact on extension profiles in sub-50-nm n-MOSFETs,” IEEE Trans. Electron Dev., 53 (11), 2755–2763, 2006.Google Scholar
  251. 251.
    D. Ha, H. Takeuchi, Y.-K. Choi, T.-J. King, D.-L. Kwong, A. Agrawal, and M. Ameen,“Molybdenum-gate HfO2 CMOS FinFET technology,” IEEE IEDM Tech. Digest, 643– 646, 2004.Google Scholar
  252. 252.
    J. Kedzierski, M. Ieong, T. Kanarsky, Y. Zhang, and H.-S. P. Wong,“Fabrication of metal gated FinFETs through complete gate silicidation with Ni,” IEEE Trans. Electron Dev., 51 (12) 2115–2120, 2004.Google Scholar
  253. 253.
    W. Xiong, C. Rinn Cleavelin, P. Kohli, C. Huffman, T. Schulz, K. Schruefer, G. Gebara, K. Mathews, P. Patruno, Y.-M. Le Vaillant, I. Cayrefourcq, M. Kennard, C. Mazure, K. Shin, and T.-J. King Liu,“Impact of Strained-Silicon-on-Insulator (sSOI) substrate on FinFET Mobility,” IEEE Electron Dev. Lett., 27 (7), 612–614, 2006.Google Scholar
  254. 254.
    K.-M. Tan, T.-Y. Liow, R. T. P. Lee, C.-H. Tung, G. S. Samudra, W.-J. Yoo, and Y.-C. Yeo,“Drive-current enhancement in FinFETs using gate-induced stress,” IEEE Electron Dev. Lett., 27 (9), 769–771, 2006.Google Scholar
  255. 255.
    K.-M. Tan, T.-Y. Liow, R. T. P. Lee, K. M. Hoe, C.-H. Tung, N. Balasubramanian, G. S. Samudra, and Y.-C. Yeo,“Strained p-channel FinFETs with extended ?-shaped silicon–germanium source and drain stressors,” IEEE Electron Dev. Lett., 28 (10), 905–908, 2007.Google Scholar
  256. 256.
    B.-Y. Tsui and C.-P. Lin,“A novel 25-nm modified Schottky-Barrier FinFET with high performance,” IEEE Electron Dev. Lett., 430–432, 2004.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Personalised recommendations