Closing the Power Gap Between ASIC & Custom pp 219-249 | Cite as

# Placement for Power Optimization

Circuit placement is a well studied area of VLSI design. The logic elements in a circuit design must be transferred onto the silicon substrate – transistors are not allowed to overlap, and there are a variety of spacing and size constraints. In this chapter, we survey techniques to minimize power within a placement context. By “placement”, we mean a mapping of each logic element to a physical location.

Minimization of power during circuit placement requires a delicate balance of constraints. There is always a trade-off between power and speed. If speed is not an issue, power can be reduced by operating at a low frequency, increasing device threshold voltages, and down-sizing devices which reduces the layout area. However for modern circuits, it’s rare to have such low performance objectives. Rather, the challenge is to design a circuit that is both fast and low power.

## Keywords

Power Optimization Placement Problem Logic Element Wire Length Placement Algorithm## Preview

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