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Placement for Power Optimization

  • Ameya R. Agnihotri
  • Satoshi Ono
  • Patrick H. Madden

Circuit placement is a well studied area of VLSI design. The logic elements in a circuit design must be transferred onto the silicon substrate – transistors are not allowed to overlap, and there are a variety of spacing and size constraints. In this chapter, we survey techniques to minimize power within a placement context. By “placement”, we mean a mapping of each logic element to a physical location.

Minimization of power during circuit placement requires a delicate balance of constraints. There is always a trade-off between power and speed. If speed is not an issue, power can be reduced by operating at a low frequency, increasing device threshold voltages, and down-sizing devices which reduces the layout area. However for modern circuits, it’s rare to have such low performance objectives. Rather, the challenge is to design a circuit that is both fast and low power.

Keywords

Power Optimization Placement Problem Logic Element Wire Length Placement Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Adya, S., et al., “Unification of partitioning, placement, and floorplanning, ” in Proc. Int. Conf. on Computer Aided Design, 2004, pp. 550-557.Google Scholar
  2. [2]
    Adya, S., Markov, I., and Villarrubia, P., “On whitespace in mixed-size placement and physical synthesis, ” in Proc. Int. Conf. on Computer Aided Design, 2003, pp. 311-318.Google Scholar
  3. [3]
    Adya, S., et al., “Benchmarking for large-scale placement and beyond, ” IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 4, 2004, pp. 472-487.CrossRefGoogle Scholar
  4. [4]
    Agnihotri, A., et al., “Fractional cut: Improved recursive bisection placement, ” in Proc. Int. Conf. on Computer Aided Design, 2003, pp. 307-310.Google Scholar
  5. [5]
    Alpert, C., et al., “The ISPD98 circuit benchmark suite, ” in Proc. Int. Symp. on Physical Design, 1998, pp. 80-85.Google Scholar
  6. [6]
    Alpert, C., Nam, G., and Villarrubia, P., “Free space management for cut-based placement, ” in Proc. Int. Conf. on Computer Aided Design, 2002, pp. 746-751.Google Scholar
  7. [7]
    Alpert, C., et al., “Placement stability metrics, ” in Proc. Asia South Pacific Design Automation Conf., 2005, pp. 1144-1147.Google Scholar
  8. [8]
    Brenner, U., Pauli, A., and Vygen, J., “Almost optimum placement legalization by mini-mum cost flow and dynamic programming, ” in Proc. Int. Symp. on Physical Design, 2004, pp. 2-9.Google Scholar
  9. [9]
    Breuer, M., “A class of min-cut placement algorithms, ” in Proc. Design Automation Conf., 1977, pp. 284-290.Google Scholar
  10. [10]
    Chang, C., Cong, J., and Xie, M., “Optimality and scalability study of existing placement algorithms, ” in Proc. Asia South Pacific Design Automation Conf., 2003, pp. 621-627.Google Scholar
  11. [11]
    Chang, J., and Pedram, M., “Power minimization using multiple supply voltages, ” in Proc. Int. Symp. on Low Power Electronic Design, 1996, pp. 157-162.Google Scholar
  12. [12]
    Chen, C., and Sarrafzadeh, M., “An effective algorithm for gate-level power-delay tradeoff using two voltages, ” in Proc. Int. Conf. on Computer Aided Design, 1999, pp. 222-227.Google Scholar
  13. [13]
    Cong, J., and Smith, M., “A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design, ” in Proc. Design Automation Conf., 1993, pp. 755-780.Google Scholar
  14. [14]
    Doll, K., Johannes, F., and Antreich, K., “Iterative placement improvement by network flow methods, ” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 10, 1994, pp. 1189-1200.CrossRefGoogle Scholar
  15. [15]
    Donath, W., et al., “Transformational placement and synthesis, ” in Proc. Design, Automation and Test in Europe Conf., 2000, pp. 194-201.Google Scholar
  16. [16]
    Donath, W., “Placement and average interconnection lengths of computer logic, ” IEEE Trans. on Circuits and Systems, vol. CAS-26, no. 4, 1979, pp. 272-277.CrossRefGoogle Scholar
  17. [17]
    Donno, M., et al., “Enhanced clustered voltage scaling for low power, ” in Proc. Great Lakes Symposium on VLSI, 2002, pp. 18-23.Google Scholar
  18. [18]
    Dreyfus, S., “An appraisal of some shortest-path algorithms, ” Operations Research, vol. 17, 1969, pp. 395-412.MATHCrossRefGoogle Scholar
  19. [19]
    Dunlop, A., et al., “Chip layout optimization using critical path weighting, ” in Proc. Design Automation Conf., 1984, pp. 133-136.Google Scholar
  20. [20]
    Dunlop, A., and Kernighan, B., “A procedure for placement of standard-cell VLSI circuits, ” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-4, no. 1, January 1985, pp. 92-98.CrossRefGoogle Scholar
  21. [21]
    Eisenmann, H., and Johannes, F., “Generic global placement and floorplanning, ” in Proc. Design Automation Conf., 1998, pp. 269-274.Google Scholar
  22. [22]
    Frankle, J., “Iterative and adaptive slack allocation for performance-driven layout, ” in Proc. Design Automation Conf., 1992, pp. 536-542.Google Scholar
  23. Hill, D., “Method and system for high speed detailed placement of cells within an integrated circuit design, ” U. S. Patent No. 6, 370, 673, Apr. 9, 2002.Google Scholar
  24. [24]
    Hu, J., et al., “Architecting voltage islands in core-based system-on-a-chip designs, ” in Proc. Int. Symp. on Low Power Electronic Design, 2004, pp. 180-185.Google Scholar
  25. [25]
    Hur, S., and Lillis, J., “Mongrel: Hybrid techniques for standard cell placement, ” in Proc. Int. Conf. on Computer Aided Design, 2000, pp. 165-170.Google Scholar
  26. [26]
    Kahng, A., Markov, I., and Reda, S., “On legalization of row-based placements, ” in Proc. Great Lakes Symposium on VLSI, 2004, pp. 214-219.Google Scholar
  27. [27]
    Kahng, A., and Reda, S., “Evaluation of placer suboptimality through zero-change netlist transformations, ” in Proc. Int. Symp. on Physical Design, 2005, pp. 208-215.Google Scholar
  28. [28]
    Kahng, A., and Wang, Q., “An analytic placer for mixed-size placement and timing-driven placement, ” in Proc. Int. Conf. on Computer Aided Design, 2004, pp. 565-572.Google Scholar
  29. [29]
    Kahng, A., and Wang, Q., “Implementation and extensibility of an analytic placer, ” in Proc. Int. Symp. on Physical Design, 2004, pp. 18-25.Google Scholar
  30. [30]
    Karypis, G., “Multilevel hypergraph partitioning: Application in VLSI domain, ” in Proc. Design Automation Conf., 1997, pp. 526-529.Google Scholar
  31. [31]
    Khatkhate, A., et al., “Recursive bisection based mixed block placement, ” in Proc. Int. Symp. on Physical Design, 2004, pp. 84-89.Google Scholar
  32. [32]
    Kirkpatrick, S., “Optimization by simulated annealing: Quantitative studies, ” J. Statistical Physics, vol. 34, 1984, pp. 975-986.CrossRefMathSciNetGoogle Scholar
  33. [33]
    Kleinhans, J., et al., “GORDIAN: VLSI placement by quadratic programming and slicing optimization, ” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 3, 1991, pp. 356-365.CrossRefGoogle Scholar
  34. [34]
    Koźmiński, K., “Benchmarks for layout synthesis -evolution and current status, ” in Proc. Design Automation Conf., 1991, pp. 265-270.Google Scholar
  35. [35]
    Lackey, D., et al., “Managing power and performance for System-on-Chip designs using voltage islands, ” in Proc. Int. Conf. on Computer Aided Design, 2002, pp. 195-202.Google Scholar
  36. [36]
    Li, C., Koh, C., and Madden, P., “Floorplan management: Incremental placement for gate sizing and buffer insertion, ” in Proc. Asia South Pacific Design Automation Conf., 2005, pp. 349-354.Google Scholar
  37. [37]
    Li, C., et al., “Routability-driven placement and white space allocation, ” in Proc. Int. Conf. on Computer Aided Design, 2004, pp. 394-401.Google Scholar
  38. [38]
    Liu, Q., and Marek-Sadowska, M., “Pre-layout wire length and congestion estimation, ” in Proc. Design Automation Conf., 2004, pp. 582-588.Google Scholar
  39. [39]
    Lou, J., Krishanmoorthy, S., and Sheng, H., “Estimating routing congestion using probabilistic analysis, ” in Proc. Int. Symp. on Physical Design, 2001, pp. 112-117.Google Scholar
  40. [40]
    Madden, P., “Reporting of standard cell placement results, ” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 2, February 2002, pp. 240-247.CrossRefGoogle Scholar
  41. [41]
    Magen, N., et al., “Interconnect-power dissipation in a microprocessor, ” in Proc. System Level Interconnect Prediction Workshop, 2004, pp. 7-13.Google Scholar
  42. [42]
    Nam, G., et al., “The ISPD2005 placement contest and benchmark suite, ” in Proc. Int. Symp. on Physical Design, 2005, pp. 216-220.Google Scholar
  43. [43]
    Ou, S., and Pedram, M., “Timing-driven placement based on partitioning with dynamic cut-net control, ” in Proc. Design Automation Conf., 2000, pp. 472-476.Google Scholar
  44. [44]
    Pedram, M., “Power minimization in IC design: Principles and applications, ” ACM Trans. on Design Automation of Electronics Systems, vol. 1, no. 1, 1996, pp. 3-56.CrossRefGoogle Scholar
  45. [45]
    Puri, R., et al., “Pushing ASIC performance in a power envelope, ” in Proc. Design Automation Conf., 2003, pp. 788-793.Google Scholar
  46. [46]
    Rohe, A., and Brenner, U., “An effective congestion driven placement framework, ” in Proc. Int. Symp. on Physical Design, 2002, pp. 1-6.Google Scholar
  47. [47]
    Sahni, S., and Bhatt, A., “The complexity of design automation problems, ” Proc. Design Automation Conference, 1980, pp. 402—411.Google Scholar
  48. [48]
    Saxena, P., et al., “Repeater scaling and its impact on CAD, ” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 4, 2004, pp. 451-463.CrossRefGoogle Scholar
  49. [49]
    Scheffer, L., and Nequist, E., “Why interconnect prediction doesn’t work, ” in Proc. System Level Interconnect Prediction Workshop, 2000, pp. 139-144.Google Scholar
  50. [50]
    Stroobandt, D., “A priori system-level interconnect prediction: Rent’s rule and wire length distribution models, ” in Proc. System Level Interconnect Prediction Workshop, 2001, pp. 3-21.Google Scholar
  51. Sutherland, I., Sproull, R., and Harris, D., Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, 1999.Google Scholar
  52. [52]
    Swartz, W., and Sechen, C., “Timing driven placement for large standard cell circuits, ” in Proc. Design Automation Conf., 1995, pp. 211-215.Google Scholar
  53. [53]
    Usami, K., and Horowitz, M., “Clustered voltage scaling technique for low-power design, ” in Proc. Int. Symp. on Low Power Electronic Design, 1995, pp. 3-9.Google Scholar
  54. [54]
    Viswanathan, N., and Chu, C., “Fastplace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model, ” in Proc. Int. Symp. on Physical Design, 2004, pp. 26-33.Google Scholar
  55. [55]
    Vujkovic, M., et al., “Efficient timing closure without timing driven placement and routing, ” in Proc. Design Automation Conf., 2004, pp. 268-273.Google Scholar
  56. [56]
    Vygen, J., “Algorithms for large-scale flat placement, ” in Proc. Design Automation Conf., 1997, pp. 746-751.Google Scholar
  57. [57]
    Wang, M., Yang, X., and Sarrafzadeh, M., “Dragon2000: Standard-cell placement tool for large industry circuits, ” in Proc. Int. Conf. on Computer Aided Design, 2000, pp. 260-263.Google Scholar
  58. [58]
    Westra, J., and Groeneveld, P., “Is probabilistic congestion estimation worthwhile?” in Proc. System Level Interconnect Prediction Workshop, 2005, pp. 99-106.Google Scholar
  59. [59]
    Yang, X., Choi, B., and Sarrafzadeh, M., “Routability driven white space allocation for fixed-die standard cell placement, ” in Proc. Int. Symp. on Physical Design, 2002, pp. 42-50.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Ameya R. Agnihotri
    • 1
  • Satoshi Ono
    • 1
  • Patrick H. Madden
    • 1
  1. 1.Computer Science Department T. J. Watson School of EngineeringState University of New YorkBinghamtonUSA

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