Linear Programming for Multi-Vth and Multi-Vdd Assignment
Having provided a strong gate sizing benchmark using only a single transistor threshold voltage (Vth) and single supply voltage (Vdd) in Chapter 6, we now examine the impact of additionally using multiple-Vth and dual Vdd to minimize power. Comparing cells with different Vth values is no different to comparing cells with different sizes, providing that the leakage is included in the total circuit power. Multiple supply voltages can also be handled similarly, with level converter overheads for restoring to high Vdd.
Our dual-Vdd/dual-Vth/sizing results achieve on average 5% to 13% power savings versus the two alternate dual-Vdd/dual-Vth/sizing optimization approaches suggested in  and . Importantly, the linear programming approach has runtimes that scale between linearly and quadratically with circuit size, whereas other algorithms that have been proposed for multi- Vdd, multi-Vth and gate size assignment have cubic runtime growth. This chapter examines in detail optimization with multiple supply voltages and multiple threshold voltages.
KeywordsThreshold Voltage Power Saving Delay Constraint Timing Slack PMOS Transistor
Unable to display preview. Download preview PDF.
- Avant!, Star-Hspice Manual, 1998, 1714 pp.Google Scholar
- Bai, M., and Sylvester, D., “Analysis and Design of Level-Converting Flip-Flops for Dual-Vdd/Vth Integrated Circuits,” IEEE International Symposium on System-on-Chip, 2003, pp. 151-154.Google Scholar
- Chinnery, D., and Keutzer, K., “Linear Programming for Sizing, Vth and Vdd Assign-ment, ” in Proceedings of the International Symposium on Low Power Electronics and Design, 2005, pp. 149-154.Google Scholar
- Kulkarni, S., and Sylvester, D., “Fast and Energy-Efficient Asynchronous Level Con-verters for Multi-VDD Design, ” IEEE Transactions on VLSI Systems, September 2004, pp. 926-936.Google Scholar
- Kulkarni, S., Srivastava, A., and Sylvester, D., “A New Algorithm for Improved VDD Assignment in Low Power Dual VDD Systems,” International Symposium on Low-Power Electronics Design, 2004, pp. 200-205.Google Scholar
- Nguyen, D., et al., “Minimization of Dynamic and Static Power Through Joint Assign-ment of Threshold Voltages and Sizing Optimization, ” International Symposium on Low Power Electronics and Design, 2003, pp. 158-163.Google Scholar
- Puri, R., et al., “Pushing ASIC Performance in a Power Envelope, ” in Proceedings of the Design Automation Conference, 2003, pp. 788-793.Google Scholar
- Sirichotiyakul, S., et al., “Stand-by Power Minimization through Simultaneous Thres-hold Voltage Selection and Circuit Sizing, ” in Proceedings of the Design Automation Conference, 1999, pp. 436-41.Google Scholar
- Srivastava, A., Sylvester, D., and Blaauw, D., “Power Minimization using Simultaneous Gate Sizing Dual-Vdd and Dual-Vth Assignment, ” in Proceedings of the Design Auto-mation Conference, 2004, pp. 783-787.Google Scholar
- Stok, L., et al., “Design Flows, ” chapter in the CRC Handbook of EDA for IC Design, CRC Press, 2006.Google Scholar
- Usami, K., and Horowitz, M., “Clustered voltage scaling technique for low power design, ” in Proceedings of the International Symposium on Low Power Design, 1995, pp. 3-8.Google Scholar
- Usami, K., et al., “Automated Low-power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor, ”, in Proceedings of the Custom Integrated Circuits Conference, 1997, pp. 131-134.Google Scholar
- Wei, L., et al., “Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications, ” in Proceedings of the Design Automation Conference, 1999, pp. 430-435.Google Scholar
- Wei, L., Roy, K., and Koh, C., “Power Minimization by Simultaneous Dual-Vth Assignment and Gate-Sizing, ” in Proceedings of the IEEE Custom Integrated Circuits Conference, 2000, pp. 413-416.Google Scholar