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Linear Programming for Multi-Vth and Multi-Vdd Assignment

  • David Chinnery
  • Kurt Keutzer

Having provided a strong gate sizing benchmark using only a single transistor threshold voltage (Vth) and single supply voltage (Vdd) in Chapter 6, we now examine the impact of additionally using multiple-Vth and dual Vdd to minimize power. Comparing cells with different Vth values is no different to comparing cells with different sizes, providing that the leakage is included in the total circuit power. Multiple supply voltages can also be handled similarly, with level converter overheads for restoring to high Vdd.

Our dual-Vdd/dual-Vth/sizing results achieve on average 5% to 13% power savings versus the two alternate dual-Vdd/dual-Vth/sizing optimization approaches suggested in [6] and [10]. Importantly, the linear programming approach has runtimes that scale between linearly and quadratically with circuit size, whereas other algorithms that have been proposed for multi- Vdd, multi-Vth and gate size assignment have cubic runtime growth. This chapter examines in detail optimization with multiple supply voltages and multiple threshold voltages.

Keywords

Threshold Voltage Power Saving Delay Constraint Timing Slack PMOS Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • David Chinnery
    • 1
  • Kurt Keutzer
    • 2
  1. 1.AMDSunnyvaleUSA
  2. 2.Department of Electrical Engineering and Computer SciencesUniversity of CaliforniaBerkeleyUSA

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