For many ASIC designs, gate sizing is the main low level design technique used to reduce power. Gate sizing is a classical circuit optimization problem for which the same basic method has been used for the past 20 years. The standard approach is to compute a sensitivity metric, for example for the power versus delay tradeoff for upsizing, and then greedily resize the gate with highest sensitivity, iterating this process until there is no further improvement. Such methods are relatively fast, with quadratic runtime growth versus circuit size, but they are known to be suboptimal. The challenge has been to find a better approach that still has fast runtimes.
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Chinnery, D., Keutzer, K. (2007). Linear Programming for Gate Sizing. In: Closing the Power Gap Between ASIC & Custom. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68953-1_6
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