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Methodology to Optimize Energy of Computation for SOCs

  • Jagesh Sanghavi
  • Eliot Gerstner

We present a novel energy optimization methodology based on processor customization. Unlike previous approaches focused either on behaviorallevel optimization with approximate consideration for underlying hardware, or register transfer level (RTL), or gate-level power optimization with limited microarchitectural trade-offs, the new approach compiles cycle count reducing instruction extension description to synthesizable hardware and accurately estimates dynamic power at the register transfer level. For a sample set of digital signal processing (DSP) applications, we see energy reductions exceeding a factor of 10× compared to fixed instruction set processors.

Keywords

Advance Encryption Standard Single Instruction Multiple Data Very Large Scale Integration Custom Instruction Cycle Count 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Jagesh Sanghavi
    • 1
  • Eliot Gerstner
    • 1
  1. 1.Santa ClaraUSA

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