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Overview of the Factors Affecting the Power Consumption

  • David Chinnery
  • Kurt Keutzer

We investigate differences in power between application-specific integrated circuits (ASICs) and custom integrated circuits, with examples from 0.6um to 0.13um CMOS. A variety of factors cause synthesizable designs to consume 3 to 7× more power. We discuss the shortcomings of typical synthesis flows, and changes to tools and standard cell libraries needed to reduce power. Using these methods, we believe that the power gap between ASICs and custom circuits can be closed to within 2.6× at a tight performance constraint for a typical ASIC design.

Keywords

Discrete Cosine Transform Leakage Power Timing Slack PMOS Transistor Dynamic Voltage Scaling 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • David Chinnery
    • 1
  • Kurt Keutzer
    • 2
  1. 1.AMDSunnyvaleUSA
  2. 2.Department of Electrical Engineering and Computer SciencesUniversity of CaliforniaBerkeleyUSA

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