Low Power ARM 1136JF-S Design

  • George Kuo
  • Anand Iyer

Methodologies for ASIC design have been seen as lagging behind custom design methodologies for a long time. With process migration to 90nm and below, ASIC design methodologies are fast catching up with custom design methodologies.

An economic driver for ASICs is the increasing demand for mobile and consumer devices. These devices have smaller form factors. They are becoming part of everyday life with high usage, and need to be robust. For example, a device that combines cellular telephony with a PDA is used many times during the day without recharging. This is forcing designers to look at power as an important metric when they design chips for these devices. Such low power designs are becoming more and more commonplace.


Dynamic Power Power Saving Level Shifter Leakage Power Test Chip 
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  1. ARM, (Realview) Core Tile for ARM1136JF-S, 2005. http://www.arm. com/products/ DevTools/Versatile/CT1136JF-S. html
  2. ARM, ARM1136 ImplementationGuide, 2002.Google Scholar
  3. ARM, ARM 1136JF-S and ARM1136J-S Technical Reference Manual, 2005. http://www.arm. com/pdfs/DDI0211F_arm1136_r1p0_trm. pdf
  4. ARM, ARM -Artisan Products: Standard Cells, 2005. http://www.artisan. com/products/ standard_cell. html
  5. Bennett, P., and Kuo, G., “ARM1136 Low Power Test Chip -case study for 90nm Low Power Implementation, ” DesignCon, Santa Clara, California, 2005, http://www. designcon. com/conference/2005/3-ta3. html
  6. Cadence, “Accurate Multi-Voltage Delay Analysis: Artisan Libraries and Cadence Encounter Digital IC Design Platform Enable Low Power Design, ” technical paper, 2004. http://www.cadence. com/datasheets/ArtisanMSMV_tp. pdf
  7. Khan, A., et al. “A 90nm Power Optimization Methodology and its Application to the ARM 1136JF-S Microprocessor, ” proceedings of the Custom Integrated Circuits Confe-ence, 2005.Google Scholar
  8. Kuo, G., and Iyer, A., “Empowering Design for Quality of Silicon: Cadence Encounter Low-Power Design Flow, ” technical paper, 2004. http://www.cadence. com/datasheets/ lowpower_tp. pdf
  9. Lackey, D., et al., “Managing Power and Performance for System-On-Chip Designs Using Voltage Islands, ” proceedings of the International Conference on Computer-Aided Design, 2002, pp. 195-202.Google Scholar
  10. Liu, R. H., “How to create designs with dynamic/adaptive voltage scaling, ” presentation at the ARM Developers’ Conference, Santa Clara, California, 2004.Google Scholar
  11. Rusu, S., “Trends and Challenges in High-Performance Microprocessor Design, ” keynote presentation at Electronic Design Processes, Monterey, California, 2004. http://www. eda. org/edps/edp04/submissions/presentationRusu. pdf

Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • George Kuo
    • 1
  • Anand Iyer
    • 1
  1. 1.Cadence Design SystemsSan JoseUSA

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