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Low Power ARM 1136JF-S Design

  • George Kuo
  • Anand Iyer

Methodologies for ASIC design have been seen as lagging behind custom design methodologies for a long time. With process migration to 90nm and below, ASIC design methodologies are fast catching up with custom design methodologies.

An economic driver for ASICs is the increasing demand for mobile and consumer devices. These devices have smaller form factors. They are becoming part of everyday life with high usage, and need to be robust. For example, a device that combines cellular telephony with a PDA is used many times during the day without recharging. This is forcing designers to look at power as an important metric when they design chips for these devices. Such low power designs are becoming more and more commonplace.

Keywords

Dynamic Power Power Saving Level Shifter Leakage Power Test Chip 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • George Kuo
    • 1
  • Anand Iyer
    • 1
  1. 1.Cadence Design SystemsSan JoseUSA

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