Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best power efficiency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-off between multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power.
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Stok, L. et al. (2007). Pushing ASIC Performance in a Power Envelope. In: Closing the Power Gap Between ASIC & Custom. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68953-1_13
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DOI: https://doi.org/10.1007/978-0-387-68953-1_13
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