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Pushing ASIC Performance in a Power Envelope

  • Leon Stok
  • Ruchir Puri
  • Subhrajit Bhattacharya
  • John Cohn
  • Dennis Sylvester
  • Ashish Srivastava
  • Sarvesh Kulkarni

Power dissipation is becoming the most challenging design constraint in nanometer technologies. Among various design implementation schemes, standard cell ASICs offer the best power efficiency for high-performance applications. The flexibility of ASICs allow for the use of multiple voltages and multiple thresholds to match the performance of critical regions to their timing constraints, and minimize the power everywhere else. We explore the trade-off between multiple supply voltages and multiple threshold voltages in the optimization of dynamic and static power.

Keywords

Threshold Voltage Supply Voltage Critical Path Leakage Power Process Corner 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Leon Stok
    • 1
  • Ruchir Puri
    • 1
  • Subhrajit Bhattacharya
    • 1
  • John Cohn
    • 1
  • Dennis Sylvester
    • 2
  • Ashish Srivastava
    • 2
  • Sarvesh Kulkarni
    • 2
  1. 1.IBM Research, Yorktown Hts, NYIBM MicroelectronicsEssex JnUSA
  2. 2.Department of Electrical Engineering and Computer ScienceUniversity of MichiganAnn ArborUSA

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