Advertisement

Power Gating Design Automation

  • Jerry Frenkil
  • Srini Venkatraman

This chapter will describe in detail the use of power gating for leakage reduction along with cell-based design automation methods employed by the CoolPowerTM design tool, and is organized as follows. The next section briefly surveys different leakage reduction techniques, providing the motivation for power gating. The subsequent sections describe design issues, CoolPower automation methods including analysis and optimization techniques, and two different power gating application flows as well as results from using those flows. This chapter then concludes with a view to the future and likely new developments in power gating design.

Keywords

Critical Path Area Overhead Leakage Power Register Transfer Level Logic Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [1]
    Anis, M., Areibi, S., and Elmasry, M., “Design and optimization of multithreshold (MTCMOS) Circuits, ” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, October 2002, pp. 1324-1342.CrossRefGoogle Scholar
  2. [2]
    von Arnim, K., et. al., “Efficiency of body biasing in 90-nm CMOS for low-power digital circuits, ” IEEE Journal of Solid State Circuits, vol. 40, no. 7, July 2005, pp. 1549-1556.CrossRefGoogle Scholar
  3. [3]
    Calhoun, B., et. al., “Power gating and dynamic voltage scaling, ” Leakage in Nanometer CMOS Technologies, S. Narendra and A. Chandraksan, editors, Springer, 2005.Google Scholar
  4. [4]
    Choi, K., Xu, Y., and Sakurai, T., “Optimal zigzag (OZ): an effective yet feasible power-gating scheme achieving two orders of magnitude lower standby leakage, ” proceedings of the Symposium on VLSI Circuits, 2005, pp. 312-315.Google Scholar
  5. [5]
    Frenkil, J., “Current scheduling system and method for optimizing multi-threshold CMOS designs, ” U. S. Patent No. 7117457, Oct. 3, 2006.Google Scholar
  6. [6]
    Frenkil, J., “Vectorless instantaneous current estimation, ” U. S. Patent No. 6807660, Oct. 19, 2004.Google Scholar
  7. [7]
    Kao, J., Miyazaki, M., and Chandrakasan, A., “A 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture, ” IEEE Journal of Solid State Circuits, vol. 37, no. 11, November 2002, pp. 1545-1554.CrossRefGoogle Scholar
  8. [8]
    Kao, J., Narendra, S., Chandrakasan, A., “MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, ” proceedings of the Design Automation Conference, 1998, pp. 495-500.Google Scholar
  9. [9]
    Kawaguchi, H., Nose, K., and Sakurai, T., “A super cut-off CMOS (SCCMOS) scheme for 0. 5-V supply voltage with picoampere stand-by current, ” IEEE Journal of Solid State Circuits, vol. 35, no. 10, October 2000, pp. 1498-1501.CrossRefGoogle Scholar
  10. [10]
    Keshavarzi, A., et. al., “Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs, ” proceedings of the International Symposium on Low Power Electro-nics and Design, 2001, pp. 207-212.Google Scholar
  11. [11]
    Keshavarzi, A., Roy, K., and Hawkins, C., “Intrinsic leakage in low power deep submicron CMOS ICs, ” International Test Conference Proceedings, 1997, pp. 146-155.Google Scholar
  12. [12]
    Kitahara, T., et. al., “Area-efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction, ” proceedings of the Design Automation and Test in Europe Conference, 2005, pp. 646-647.Google Scholar
  13. [13]
    Kosonocky, S., et. al., “Enhanced multi-threshold (MTCMOS) circuits using variable well bias, ” proceedings of the International Symposium on Low Power Electronics and Design, 2001, pp. 165-169.Google Scholar
  14. [14]
    Lackey, D., et. al., “Managing Power and Performance for System-on-Chip Designs using Voltage Islands, ” proceedings of the International Conference on Computer-Aided Design, 2002, pp. 192-202.Google Scholar
  15. Liu, W., et. al., “BSIM3v3. 2. 2 MOSFET Model User’s Manual, ” Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, technical report no. UCB/ERL M99/18.Google Scholar
  16. [16]
    Martin, S., et al., “Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads, ” proceedings of the International Conference on Computer-Aided Design, 2002, pp. 721-725.Google Scholar
  17. [17]
    Min, K., Kawaguchi, H., and Sakurai, T., “Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era, ” proceedings of the International Solid State Circuits Conference, 2003, pp. 400-401.Google Scholar
  18. [18]
    Mutoh, S., et. al., “1-V power supply high-speed digital circuit technology with multi-threshold-voltage CMOS, ” IEEE Journal of Solid State Circuits, vol. 30, no. 8, August 1995, pp. 847-853.CrossRefGoogle Scholar
  19. Semiconductor Industry Association, The International Technology Roadmap for Semi-conductors, 2003.Google Scholar
  20. [20]
    Sirichotiyakul, S., et al., “Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing, ” proceedings of the Design Automation Conference, 1999, pp. 436-441.Google Scholar
  21. Taiwan Semiconductor Manufacturing Company, “Fine Grain MTCMOS Design Metho-dology, ” TSMC Reference Flow Release 6. 0, 2005.Google Scholar
  22. [22]
    Tschanz, J., et. al., “Dynamic sleep transistor and body bias for active leakage power control of microprocessors, ” IEEE Journal of Solid State Circuits, vol. 38, no. 11, November 2003, pp. 1838-1845.CrossRefGoogle Scholar
  23. [23]
    Usami, K., et. al., “Automated selective multi-threshold design for ultra-low standby applications, ” proceedings of the International Symposium on Low Power Electronics and Design, 2002, pp. 202-206.Google Scholar
  24. [24]
    Uvieghara, G., et al., “A highly-integrated 3G CDMA2000 1X cellular baseband chip with GSM/AMPS/GPS/Bluetooth/multimedia capabilities and ZIF RF support, ” procee-dings of the International Solid State Circuits Conference, 2004, pp. 422-423.Google Scholar
  25. [25]
    Wang, Q., and Vrudhula, S., “Algorithms for minimizing standby power in deep sub-micrometer, dual-Vt CMOS circuits, ” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 3, March 2002, pp 306-318.CrossRefGoogle Scholar
  26. [26]
    Wei, L., et al., “Design and optimization of low voltage high performance dual threshold CMOS circuits, ” proceedings of the Design Automation Conference, 1998, pp. 489-494.Google Scholar
  27. [27]
    Won, H., et al., “An MTMCOS design methodology and its application to mobile com- puting, ” proceedings of the International Symposium on Low Power Electronics and Design, 2003, pp. 110-115.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Jerry Frenkil
    • 1
  • Srini Venkatraman
    • 1
  1. 1.Sequence DesignWestfordUSA

Personalised recommendations