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Introduction

  • David Chinnery
  • Kurt Keutzer

This book examines the power consumption of ASIC and custom interated- circuits. In particular, we examine the relationship between custom circuits designed without any significant restriction in design methodology and ASIC circuits designed in a high-productivity EDA tool methodology. From analysis of similar ASIC and custom designs, we estimate that the power consumption of typical ASICs may be 3 to 7× that of custom ICs fabricated in process technology of the same generation. We consider ways to augment and enhance an ASIC methodology to bridge this power gap between ASIC and custom.

Keywords

Field Programmable Gate Array Logic Gate Custom Design PMOS Transistor ASIC Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Chinnery, D., and Keutzer, K., Closing the Gap Between ASIC & Custom: Tools and Techniques for High-Performance ASIC Design, Kluwer Academic Publishers, 2002, 432 pp.Google Scholar
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    Keutzer, K. et al., “System-level Design: Orthogonalization of Concerns and Platform-Based Design, ” IEEE Transactions on Computer-Aided Design, vol. 19, no. 12, December 2000, pp. 1523-1543.CrossRefGoogle Scholar
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    Kuon, I., and Rose, J., “Measuring the Gap Between FPGAs and ASICs, ” International Symposium on Field Programmable Gate Arrays, 2006, pp. 21-30.Google Scholar
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    Smith, D., HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simu-lating ASICs and FPGAs Using VHDL or Verilog, Doone Publications, 1998, 464 ppGoogle Scholar
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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • David Chinnery
    • 1
  • Kurt Keutzer
    • 2
  1. 1.AMDSunnyvaleUSA
  2. 2.Department of Electrical Engineering and Computer SciencesUniversity of CaliforniaBerkeleyUSA

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