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K. Hardee, F. Jones, D. Butler, M. Parris, M. Mound, H. Calendar, G. Jones, L. Aldrich, C. Gruenschlaeger, M. Miyabayashi, K. Taniguchi, and T. Arakawa, “A 0.6V 205MHz 19.5ns tRC 16Mb embedded DRAM,” ISSCC Dig. Tech. Papers, pp. 200–201, Feb. 2004.
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, NY, 2001.
Y. Nakagome, M. Horiguchi, T. Kawahara, K. Itoh, “Review and future prospects of low-voltage RAM circuits,” IBM J. R & D, vol. 47, no. 5/6, pp. 525–552, Sep./Nov. 2003.
K. Itoh, K. Osada, and T. Kawahara, “Reviews and future prospects of low-voltage embedded RAMs,” CICC Dig. Tech. Papers, pp. 339–344, Oct. 2004.
M. Aoki, J. Etoh, K. Itoh, S. Kimura and Y. Kawamoto, “A 1.5V DRAM for battery-based applications,” ISSCC Dig. Tech. Papers, pp. 238–239, Feb 1989.
Y. Nakagome, Y. Kawamoto, H. Tanaka, K. Takeuchi, E. Kume, Y. Watanabe, T. Kaga, F. Murai, R. Izawa, D. Hisamoto, T. Kisu, T. Nishida, E. Takeda and K. Itoh, “A 1.5-V circuit technology for 64Mb DRAMs,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 17–18, June 1990.
K. Itoh, “Reviews and prospects of deep sub-micron DRAM technology,” SSDM Ext. Abst., pp. 468–471, Aug. 1991.
J. Etoh, K. Itoh, Y. Kawajiri, Y. Nakagome, E. Kume and H. Tanaka, “Large scale integrated circuit for low voltage operation,” US Patent No. 5297097 (Mar. 1994), RE37593 (Mar. 2002).
Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi and M. Aoki, “Sub-1-V swing bus architecture for future low-power ULSIs,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 82–83, June 1992.
T. Kawahara, M. Horiguchi, Y. Kawajiri, G. Kitsukawa, T. Kure and M Aoki, “Subthreshold current reduction for decoded-driver by self-reverse biasing,” IEEE J. Solid-State Circuits, vol. 28, pp. 1136–1144, Nov. 1993.
M. Horiguchi, T. Sakata and K. Itoh, “Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI’s,” IEEE J. Solid-State Circuits, vol. 28, pp. 1131–1135, Nov. 1993.
D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, K. Ohuchi and H. Tango, “Standby/active mode logic for sub-1-V operating ULSI memory,” IEEE J. Solid-State Circuits, vol. 29, pp. 441–447, Apr. 1994.
T. Sakata, M. Horiguchi, and K. Itoh, “Subthreshold-current Reduction Circuits for Multi-gigabit DRAMs,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 45–46, May 1993.
T. Sakata, K. Itoh, M. Horiguchi and M. Aoki, “Subthreshold-current reduction circuits for multi-gigabit DRAM’s,” IEEE J. Solid-State Circuits, vol. 29, No.7, pp. 761–769, July 1994.
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada, “1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE J. Solid-State Circuits, vol. 30, pp. 847–854, Aug. 1995.
K. Itoh, “Reviews and prospects of low-power memory circuits” (invited), Low-Power CMOS Design, A. Chandrakasan and R. Brodersen, Eds., Wiley–IEEE Press, NJ, pp. 313–317, 1998.
M. Hasegawa, M. Nakamura, S. Narui, S. Ohkuma, Y. Kawase, H. Endoh, S. Miyatake, T. Akiba, K. Kawakita, M. Yoshida, S. Yamada, T. Sekiguchi, I. Asano, Y. Tadaki, R. Nagai, S. Miyaoka, K. Kajigaya, M. Horiguchi and Y. Nakagome, “A 256Mb SDRAM with subthreshold leakage current suppression,” ISSCC Dig. Tech. Papers, pp. 80–81, Feb. 1998.
S. Narendra, S. Borkar, V. De, D. Antoniadis and A. Chandrakasan, “Scaling of stack effect and its application for leakage reduction,” Proc. ISLPED, pp. 195–199, Aug. 2001.
C. Akrout, J. Bialas, M. Canada, D. Cawthron, J. Corr, B. Davari, R. Floyd, S. Geissler, R. Goldblatt, R. Houle, P. Kartschoke, D. Kramer, P. McCormick, N. Rohrer, G. Salem, R. Schulz, L. Su and L. Whitney, “A 480-MHz RISC microprocessor in a 0.12-um Leff CMOS technology with copper interconnects,” IEEE J. Solid-State Circuits, vol. 33, pp. 1609–1616, Nov. 1998.
H. Morimura and N. Shibata, “A 1-V 1-Mb SRAM for portable equipment,” Proc. ISLPED, pp. 61–66, Aug. 1996.
K. Itoh, R. Hori, H. Masuda, Y. Kawajiri, H. Kawamoto and H. Katto, “A single 5V 64K dynamic RAM,” ISSCC Dig. Tech. Papers, pp. 228–229, Feb. 1980.
I. Fukushi, R. Sasagawa, M. Hamaminato, T. Izawa and S. Kawashima, “A low-power SRAM using improved charge transfer sense amplifiers and a dual-Vth CMOS circuit scheme,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 142–145, June 1998.
A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry, T. Ghani, S. Borkar and V. De, “Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs,” Proc. ISLPED, pp. 207–212, Aug. 2001.
H. Mizuno, K. Ishibashi, T. Shimura, T. Hottori, S. Narita, K. Shiozawa, S. Ikeda and K. Uchiyama, “A 18-µ A standby current 1.8-V 200-MHz microprocessor with self-substrate-biased data-retention mode,” IEEE J. Solid-State Circuits, vol. 34, pp. 1492–1500, Nov. 1999.
T. Sakata, M. Horiguchi, M. Aoki and K. Itoh, “Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAMs,” Proc. ESSCIRC, pp. 131–134, Sep. 1993.
K. Seta, H. Hara, T. Kuroda, M. Kakumu and T. Sakurai, “50% active-power saving without speed degradation using standby power reduction (SPR) circuit,” ISSCC Dig. Tech. Papers, pp. 318–319, Feb. 1995.
K. Kumagai, H. Iwaki, H. Yoshida, H. Suzuki, T. Yamada and S. Kurosawa, “A novel powering-down scheme for low Vt CMOS circuits,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 44–45, June 1998.
M. Mizuno, K. Furuta, S. Narita, H. Abiko, I. Sakai and M. Yamashina, “Elastic-Vt CMOS circuits for multiple on-chip power control,” ISSCC Dig. Tech. Papers, pp. 300–301, Feb. 1996.
G. Kitsukawa, M. Horiguchi, Y. Kawajiri, T. Kawahara, T. Akiba, Y. Kawase, T. Tachibana, T. Sakai, M. Aoki, S. Shukuri, K. Sagara, R. Nagai, Y. Ohji, N. Hasegawa, N. Yokoyama, T. Kisu, H. Yamashita, T. Kure and T. Nishida, “256-Mb DRAM circuit technologies for file applications,” IEEE J. Solid-State Circuits, vol. 28, pp. 1105–1113, Nov. 1993.
M. Yamaoka, Y. Shinozaki, N. Maeda, Y. Shimazaki, K. Kato, S. Shimada, K. Yanagisawa, and K. Osada, “A 300MHz 25µA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor,” ISSCC Dig. Tech. Papers, pp. 494–495, Feb. 2004.
J. P. Halter and F. N. Najm, “A gate-level leakage power reduction method for ultra-low-power CMOS circuits,” Proc. CICC, pp. 475–478, May 1997.
K-S Min, H. Kawaguchi, and T. Sakurai, “Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era,” ISSCC Dig. Tech. Papers, pp. 400–401, Feb. 2003.
H. Kawaguchi, K. Nose and T. Sakurai, “A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current,” IEEE J. Solid-State Circuits, vol. 35, pp. 1498–1501, Oct. 2000.
T. Kawahara and K. Itoh, “Memory Leakage Reduction,” Chapter in Leakage in Nanometer CMOS Technologies, Edited by S. G. Narendra and A. Chandrakasan, Springer, 2006.
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Itoh, K., Horiguchi, M., Tanaka, H. (2007). Leakage Reduction for Logic Circuits in RAMs. In: Itoh, K., Horiguchi, M., Tanaka, H. (eds) Ultra-Low Voltage Nano-Scale Memories. Series On Integrated Circuits And Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68853-4_4
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