This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Reference
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, NY, 2001.
Y. Nakagome, M. Horiguchi, T. Kawahara, K. Itoh, “Review and future prospects of low-voltage RAM circuits,” IBM J. R&D, vol. 47, no. 5/6, pp. 525–552, Sep./Nov. 2003.
K. Itoh, K. Osada, and T. Kawahara, “Reviews and future prospects of low-voltage embedded RAMs,” CICC Dig. Tech. Papers, pp. 339–344, Oct. 2004.
K. Itoh, “Low-voltage embedded RAMs in the nanometer era,” ICICDT Dig. Tech. Papers, 235–242, May 2005.
S. Naffziger, B. Stackhouse, and T. Grutkowski, “The implementation of a 2-core multi-threaded Itanium®-family processor,” ISSCC Dig. Tech. Papers, pp. 182–183, Feb. 2005.
S-M Jung, J. Jang, W. Cho, J. Moon, K. Kwak, B. Choi, B. Hwang, H. Lim, J. Jeong, J. Kim, and K. Kim, “The revolutionary and truly 3-dimensional 25F2 SRAM technology with the smallest S3 (Stacked Single-crystal Si) cell, 0.16µm2, and SSTFT (Stacked Single-crystal Thin Film Transistor) for ultra high density SRAM,” Symp. VLSI Tech. Dig. Tech. Papers, pp. 228–229, June 2004.
H-J An, H-Y Nam, H-S Mo, J-P Son, B-T Lim, S-B Kang, G-H Han, J-M Park, K-H Kim, S-Y Kim, C-K Kwak, and H-G Byun, “64Mb mobile stacked single-crystal Si SRAM(S3RAM) with selective dual pumping scheme (SDPS) and multi cell burn-in scheme (MCBS) for high density and low power SRAM,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 282–283, June 2004.
Y. H. Suh, H. Y. Nam, S. B. Kang, B. G. Choi, H. S. Mo, G. H. Han, H. K. Shin, W. R. Jung, H. Lim, C. K. Kwak, and H. G. Byun, “A 256 Mb synchronous-burst DDR SRAM with hierarchical bit-line architecture for mobile applications,” ISSCC Dig. Tech. Papers, pp. 476–477, Feb. 2005.
K. Noda, K. Matsui, K. Imai, K. Inoue, K. Takashiki, H. Kawamoto, K. Yoshida, K. Takada, N. Nakamura, T. Kimura, H. Toyoshima, Y. Koishikawa, S. Maruyama, T. Saitoh, and T. Tanigawa, “A 1.9-µm2 loadless CMOS four-transistor SRAM cell in a 0.18-µm logic technology,” IEDM Dig. Tech. Papers, pp. 643–646, Dec. 1998.
K. Takeda, Y. Aimoto, N. Nakamura, H. Toyoshima, T. Iwasaki, K. Noda, K. Matsui, S. Itoh, S. Masuoka, T. Horiuchi, A . Nakagawa, K. Shimogawa, and H. Takahashi, “A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro,” IEEE J. Solid-State Circuits, Vol. 35, no. 11, pp. 1631–1640, Nov. 2000.
K. Takeda, Y. Hagihara, Y. Arimoto, M. Nomura, Y. Nakazawa, T. Ishii, and H. Kobatake, “A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications,” ISSCC Dig. Tech. Papers, pp. 478–479, Feb. 2005.
K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, “16.7fA/cell tunnel-leakage-suppressed 16-Mbit SRAM based on electric-field-relaxed scheme and alternate ECC for handling cosmic-ray-induced multi-errors”, ISSCC Dig. Tech Papers, pp. 302–303, Feb. 2003.
K. Itoh and H. Mizuno, “Low-voltage embedded-RAM technology: present and future,” Proc. 11th IFIP Int’l Conf. VLSI, pp. 393–398, Dec. 2001.
R. Tsuchiya, M. Horiuchi, S. Kimura, M. Yamaoka, T. Kawahara, S. Maegawa, T. Ipposhi, Y. Ohji, and H. Matsuoka, “Silicon on thin BOX: a new paradigm of the CMOSFET for low-power and high-performance application featuring wide-range back-bias control,” IEDM Dig. Tech. Papers, pp. 631–634, Dec. 2004.
M. Yamaoka, K. Osada, R. Tsuchiya, M. Horiuchi, S. Kimura, and T. Kawahara, “Low power SRAM menu for SOC application using yin-yang-feedback memory cell technology,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 288–291, June 2004.
P. M. Carter and B. R. Wilkins, “Influences on soft error rates in static RAM’s,” IEEE J. Solid- State Circuits, vol. sc-22, No. 3, pp. 430–436, June 1987.
S-M Jung, H. Lim, W. Cho, H. Cho, H. Hong, J. Jeong, S. Jung, H. Park, B. Son, Y. Jang, and K. Kim, “Soft error immune 0.46 µm2 SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM,” IEDM Tech. Dig., pp. 289–292, Dec. 2003.
K. Osada, K. Yamaguchi, Y. Saitoh, and T. Kawahara, “SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect,” IEEE J. Solid-State Circuits, vol. 39, No. 5, pp. 827–833, May 2004.
M. Horiguchi, M. Aoki, Y. Nakagome, S. Ikenaga, and K. Shimohigashi, “An experimental large-capacity semiconductor file memory using 16-level/cell storage,” IEEE J. Solid-State Circuits, Vol. 23, no. 1, pp. 27–33, Feb. 1988.
H. L. Kalter, C. H. Stapper, J. E. Barth, Jr., J. DiLorenzo, C. E. Drake, J. A. Fifield, G. A. Kelley, Jr., S. C. Lewis, W. B. V. D. Hoeven, and J. A. Yankosky, “A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC,” IEEE J. Solid-State Circuits, vol. 25, pp. 1118–1128, Oct. 1990.
M. Khellah, N.S. Kim, J. Haward, G. Ruhl, M. Sunna, Y. Ye, J. Tschanz, D. Somasekhar, N. Borkar, F. Hamzaoglu, G. Pandya, A. Farhang, K. Zhang, and V. De, “A 4.2 GHz 0.3 mm2 256kb dual-VCC SRAM building block in 65nm CMOS,” ISSCC Dig. Tech. Papers, pp. 624–625, Feb. 2006.
K. Osada, J-U Shin, M. Khan, Y-de Liou, K. Wang, K. Shoji, K. Kuroda, S. Ikeda, and K. Ishibashi, “Universal-VDD 0.65–2.0V 32kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric Cell,” ISSCC, Dig. Tech. Papers, pp. 168–169, Feb. 2001.
K. Itoh, A. R. Fridi, A. Bellaouar, and M. I. Elmasry, “A deep sub-V, single power-supply SRAM cell with multi-Vt, boosted storage node and dynamic load,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 132–133, June 1996.
M. Yamaoka, Y. Shinozaki, N. Maeda, Y. Shimazaki, K. Kato, S. Shimada, K. Yanagisawa, and K. Osada, “A 300MHz 25µA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor,” ISSCC Dig. Tech. Papers, pp. 494–495, Feb. 2004.
K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, and M. Bohr, “A 3-GHz 70Mb SRAM in 65nm CMOS technology with integrated column-based dynamic power supply,” ISSCC Dig. Tech. Papers, pp. 474–475, Feb. 2005.
M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, “Low-power embedded SRAM modules with expanded margins for writing,” ISSCC Dig. Tech. Papers, pp. 480–481, Feb. 2005.
F. Assaderaghi, S. Parke, P. K. Ko, and C. Hu, “A novel silicon-on-insulator (SOI) MOSFET for ultralow voltage operation,” Symp. Low Power Electronics Dig. Tech. Papers, pp. 58–59, 1994.
M. Yamaoka, K. Osada, K. Itoh, R. Tsuchiya, and T. Kawahara, “Dynamic-Vt, dual-power-supply SRAM cell using D2G-SOI for low-power SoC application,” Int’l SOI Conf. Dig., pp. 109–111, Oct. 2004.
M. Yamaoka, R. Tsuchiya, and T. Kawahara, “SRAM circuit with expanded operating margin and reduced stand-by leakage current using thin-BOX FD-SOI transistors,” A-SSCC Dig. Tech. Papers, pp. 109–112, Nov. 2005.
T. C. Chen, “Where CMOS is going: trendy hype vs. real technology,” ISSCC Dig. Tech. Papers, pp. 22–28, Feb. 2006.
C-Ho Lee, J-M Yoon, C. Lee, K. Kim, S. B. Park, Y. J. Ahn, H. S. Kang, and D. Park, “The application of BT-FinFET technology for sub 60nm DRAM integration,” ICICDT Dig. Tech. Papers, pp. 37–41, May 2005.
J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. leong, and W. Haensch, “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” IEDM Dig. Tech. Papers, pp. 247–250, Dec. 2002.
E. Ibe, “Current and future trend on cosmic-ray-neutron induced single event upset at the ground down to 0.1-micron-devices,” The Svedberg Laboratory Workshop on Applied Physics, Uppsala, May 3, 2001.
E. Seevinck, F. J. List, and J. Lohstroh, “Static-noise margin analysis of MOS SRAM cells,” IEEE J. Solid-State Circuits, Vol. SC-22, No.5, pp.748–754, Oct.1987.
T. Douseki and S. Mutoh, “Static-noise margin analysis for a scaled-down CMOS memory cell,” IEICE Trans. on Electronics, Vol. J75-C-II, No. 7, pp. 350–361, July 1992 (in Japanese).
T. Sakurai, A. Matsuzawa, and T. Douseki, Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications, Springer, 2006.
R. V. Joshi, Y. Chan, D. Plass, T. Charest, R. Freese, R. Sautter, W. Huott, U. Srinivasan, D. Rodko, P. Patel, P. Shephard, and T. Werner, “A low power and high performance SOI SRAM circuit design with improved cell stability,” Int’l SOI Conf. Dig., pp. 4–7, Oct. 2006.
K. Itoh, M. Yamaoka, and T. Kawahara, “Impact of FD-SOI on deep sub-100-nm CMOS LSIs-a view of memory designers-” Int’l SOI Conf. Dig., pp. 103–104, Oct. 2006.
R. Takemura, K. Itoh, and T. Sekiguchi, “A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers,” ISLPED Dig. Tech. Papers, pp. 123–126, Oct. 2006.
C. M. Hsieh, P. C. Murley, and R. R. O’brien, “A Field-funneling effect on the collection of alpha-particle-generated carriers in silicon devices,” IEEE Electron Device Letters, Vol. EDL-2, No.4, pp.103–105, April 1981.
K. Osada, Y. Saitoh, E. Ibe, and K. Ishibashi, “16.7-fA/cell tunnel-leakage-suppressed 16-Mbit SRAM for handling cosmic-ray-induced multi-errors,” IEEE J. Solid-State Circuits, Vol. 38, no. 11, pp. 1952–1957, Nov. 2003.
K.-H. Kim, U. Kang, H.-J. Chung, D.-H. Park, W.-S. Kim, Y.-C. Jang, M. Park, H. Lee, J.-Y. Kim, J. Sunwoo, H.-W. Park, H.-K. Kim, S.-J. Chung, J.-K. Kim, H.-S. Kim, K.-W. Kwon, Y.-T. Lee, J. S. Choi, and C. Kim, “An 8Gb/s/pin 9.6ns row-cycle 288Mb deca-data rate SDRAM with an I/O error-detection scheme,” ISSCC Dig. Tech. Papers, pp. 156–157, Feb. 2006.
K. Itoh, M. Horiguchi, and T. Kawahara, “Ultra-low voltage nano-scale embedded RAMs,” ISCAS Proc., pp.25–28, May 2006.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2007 Springer Science+ Business Media, LLC
About this chapter
Cite this chapter
Itoh, K., Horiguchi, M., Tanaka, H. (2007). Ultra-Low Voltage Nano-Scale SRAM Cells. In: Itoh, K., Horiguchi, M., Tanaka, H. (eds) Ultra-Low Voltage Nano-Scale Memories. Series On Integrated Circuits And Systems. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-68853-4_3
Download citation
DOI: https://doi.org/10.1007/978-0-387-68853-4_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-33398-4
Online ISBN: 978-0-387-68853-4
eBook Packages: EngineeringEngineering (R0)