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APlace: A High Quality, Large-Scale Analytical Placer

  • Andrew B. Kahng
  • Sherief Reda
  • Qinke Wang
Part of the Series on Integrated Circuits and Systems book series (ICIR)

Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to mention in the list of complexities.With these complexities in mind, placers are faced with the burden of finding an arrangement of placeable objects under strict wirelength, timing, and power constraints. In this chapter, we describe the architecture and novel details of our high quality, large-scale analytical placer APlace2 (and the subsequent APlace3) [26–28]. The performance of APlace2, has been recognized in the recent ISPD-2005 placement contest, and in this paper we disclose many of the technical details that we believe are key factors to its performance. We describe (1) a new clustering architecture, (2) a dynamically adaptive analytical solver, and (3) better legalization schemes and novel detailed placement methods. We also provide extensive experimental results on a number of benchmark sets, including the IBM ISPD’04, IBM-PLACE 2.0, ICCAD’04, ISPD’05, PEKO’05, ISPD’06, PEKO’06 as well as using the zero-change netlist transformation benchmarking framework.

Keywords

Dynamic Programming Algorithm Placement Problem Physical Design Cluster Hierarchy Placeable Object 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Andrew B. Kahng
  • Sherief Reda
  • Qinke Wang

There are no affiliations available

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