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Locality and Utilization in Placement Suboptimality

  • Jason Cong
  • Michalis Romesis
  • Joseph R. Shinnerl
  • Kenton Sze
  • Min Xie
Part of the Series on Integrated Circuits and Systems book series (ICIR)

Placement is a critical step in VLSI design. Interconnect delay dominates system performance, and placement determines the interconnect more than any other step in physical design. The complexity of modern designs, however, makes estimation of suboptimality difficult [14, 16, 28]. Studies on simplified, synthetic benchmarks with known optimal-wire length placements (PEKO [7]) initially suggested that many leading tools may produce solutions with excess wire length from 60% up to 150% or more. These results have generated wide interest in both industry [13] and academia [19, 22, 28]. Recent progress in placement [1, 5, 6, 17] has reduced the wire length gap on PEKO to about 12–40%.

Keywords

Grid Cell Standard Cell Wire Length White Space Terminal Vertex 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Jason Cong
  • Michalis Romesis
  • Joseph R. Shinnerl
  • Kenton Sze
  • Min Xie

There are no affiliations available

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