Advertisement

mPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control

  • Tony F. Chan
  • Kenton Sze
  • Joseph R. Shinnerl
  • Min Xie
Part of the Series on Integrated Circuits and Systems book series (ICIR)

mPL6 consists of three basic ingredients: global placement by multilevel nonlinear programming [21], discrete graph-based macro legalization followed by linear-time scan-based standard-cell legalization [26], and detailed placement [26]. It is designed for speed and scalability, low wirelength results, adaptability to complex constraints, and robustness under low white space.

Keywords

Congestion Control Coarse Level Physical Design Constraint Graph Placement Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    S.N. Adya, S. Chaturvedi, D.A. Papa J.A. Roy, and I.L. Markov. Unification of partitioning, floorplanning and placement. In Proceedings of the International Conference on Computer Aided Design, pages 550-557, Nov 2004Google Scholar
  2. 2.
    C.R. Anderson and C. Elion. Accelerated solutions of nonlinear equations using stabilized runge-kutta methods. Report, UCLA CAM, Apr 2004Google Scholar
  3. 3.
    C. Alpert, J.-H. Huang, and A.B. Kahng. Multilevel circuit partitioning. In Proceedings of the Design Automation Conference, pages 627-632, 1997Google Scholar
  4. 4.
    K. Arrow, L. Huriwicz, and H. Uzawa. Studies in Nonlinear Programming. Stanford University Press, 1958Google Scholar
  5. 5.
    C. Alpert, A.B. Kahng, G. Nam, S. Reda, and P. Villarrubia. A semi-persistent clustering technique for vlsi circuit placement. In Proceedings of the International Symposium on Physical Design, pages 200-207, Apr 2005Google Scholar
  6. 6.
    S.N. Adya and I.L. Markov. Consistent placement of macro-blocks using floorplanning and standard-cell placement. In Proceedings of the International Symposium on Physical Design, pages 12-17, Apr 2002Google Scholar
  7. 7.
    S.N. Adya, I.L. Markov, and P. G. Villarrubia. On whitespace and stability in mixed-size placement. In Proceedings of the International Conference on Computer Aided Design, pages 311-318, Nov 2003Google Scholar
  8. 8.
    A.R. Agnihotri, S. Ono, and P.H. Madden. Recursive bisection placement: Feng shui 5.0 implementation details. In Proceedings of the International Symposium on Physical Design, pages 230-232, Apr 2005Google Scholar
  9. 9.
    D.P. Bertsekas. Constrained Optimization and Lagrange Multiplier Methods. Academic Press, New York, 1982MATHGoogle Scholar
  10. 10.
    W.L. Briggs, S.F. McCormick, and V.E. Henson. A Multigrid Tutorial. SIAM, Philadelphia, second edition, 2000MATHGoogle Scholar
  11. 11.
    Ulrich Brenner, Anna Pauli, and Jens Vygen. Almost optimum placement legalization by minimum cost flow and dynamic programming. In Proceedings of the International Symposium on Physical Design, pages 2-9, April 2004Google Scholar
  12. 12.
    A. Brandt and D. Ron. Multigrid Solvers and Multilevel Optimization Strategies, chapter 1 of Multilevel Optimization and VLSICAD. Kluwer Academic Publishers, Boston, 2002Google Scholar
  13. 13.
    A. Brandt. Algebraic multigrid theory: The symmetric case. Appl. Math. Comp., 19: 23-56, 1986MATHCrossRefMathSciNetGoogle Scholar
  14. 14.
    A. Brandt. Multiscale scientific computation: Review 2001. In T. Barth, R. Haimes, and T. Chan, editors, Multiscale and Multiresolution Methods. Springer Verlag, 2001Google Scholar
  15. 15.
    T.F. Chan, J. Cong, T. Kong, J. Shinnerl, and K. Sze. An enhanced multilevel algorithm for circuit placement. In Proceedings of the International Conference on Computer Aided Design, pages 299-306, San Jose, CA, Nov 2003Google Scholar
  16. 16.
    T.F. Chan, J. Cong, T. Kong, and J. Shinnerl. Multilevel optimization for large-scale circuit placement. In Proceedings of the International Conference on Computer Aided Design, pages 171-176, San Jose, CA, Nov 2000Google Scholar
  17. 17.
    T.F. Chan, J. Cong, T. Kong, and J. Shinnerl. Multilevel Circuit Placement, chapter 4 of Multilevel Optimization in VLSICAD. Kluwer Academic Publishers, Boston, 2003Google Scholar
  18. 18.
    R. Chan, T. Chan, M.K. Ng, and A. Yip. Cosine transform preconditioner for high resolution image reconstruction. Linear Algebra and its Applications, 316:89-104, 2000MATHCrossRefMathSciNetGoogle Scholar
  19. 19.
    T.F. Chan, J. Cong, M. Romesis, J.R. Shinnerl, K. Sze, and M. Xie. mPL6: a robust multilevel mixed-size placement engine. In Proceedings of the International Symposium on Physical Design, pages 227-229, Apr 2005Google Scholar
  20. 20.
    T. Chan, J. Cong, J. Shinnerl, K. Sze, and M. Xie. Enhanced robustness in multilevel mixed-size placement. In SRC TECHCON, Oct 2005Google Scholar
  21. 21.
    T. Chan, J. Cong, and K. Sze. Multilevel generalized force-directed method for circuit placement. In Proceedings of the International Symposium on Physical Design, pages 185-192, Apr 2005Google Scholar
  22. 22.
    C.C. Chang, J. Cong, and X. Yuan. Multi-level placement for large-scale mixed-size ic designs. In Proceedings of the Asia South Pacific Design Automation Conference, pages 325-330, 2003Google Scholar
  23. 23.
    J. Cong and S.K. Lim. Edge separability-based circuit clustering with application to multi-level circuit partitioning. IEEE Tran. on Computer-Aided Design of Integrated Circuits and Systems, 23(3):346-357, 2004CrossRefGoogle Scholar
  24. 24.
    Jason Cong, Michail Romesis, and Joseph Shinnerl. Robust mixed-size placement under tight white-space constraints. In Proceedings of the International Conference on Computer Aided Design, pages 165-173, November 2005Google Scholar
  25. 25.
    Meszaros Csaba. Fast cholesky factorization for interior point methods of linear programming. Computers and Mathematics with Applications, 31:49-51, 1996MATHCrossRefMathSciNetGoogle Scholar
  26. 26.
    J. Cong and M. Xie. A robust detailed placement for mixed-size ic designs. In Proceedings of the Asia South Pacific Design Automation Conference, pages 188-194, Jan 2006Google Scholar
  27. 27.
    K. Doll, F.M. Johannes, and K.J. Antreich. Iterative placement improvement by network flow methods. IEEE Transactions on Computer-Aided Design, 13(10), October 1994Google Scholar
  28. 28.
    Hans Eisenmann and Frank M. Johannes. Generic global placement and floorplanning. In Proceedings of the Design Automation Conference, pages 269-274, 1998Google Scholar
  29. 29.
    L.C. Evans. Partial Differential Equations. American Mathematical Society, 2002Google Scholar
  30. 30.
  31. 31.
    A.V. Fiacco and G. P. McCormick. Nonlinear Programming: Sequential Unconstrained Minimization Techniques. John Wiley and Sons, Inc., New York, London, Sydney and Toronto, 1968MATHGoogle Scholar
  32. 32.
    Dwight Hill. Method and system for high speed detailed placement of cells within an integrated circuit design. US Patent No. 6,370,673, 2002Google Scholar
  33. 33.
    S.-W. Hur and J. Lillis. Mongrel: Hybrid techniques for standard-cell placement. In Proceedings of the International Conference on Computer Aided Design, pages 165-170, San Jose, CA, Nov 2000Google Scholar
  34. 34.
    B. Hu and M. Marek-Sadowska. Fine granularity clustering for large scale placement problems. IEEE Tran. on Computer-Aided Design of Integrated Circuits and Systems, 23(4):527-536, 2004CrossRefGoogle Scholar
  35. 35.
    G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: Application in vlsi domain. In Proceedings of the Design Automation Conference, pages 526-529, 1997Google Scholar
  36. 36.
    Ateen Khatkhate, Chen Li, Ameya R. Agnihotri, Mehmet C. Yildiz, Satoshi Ono, Cheng-Kok Koh, and Patrick H. Madden. Recursive bisection based mixed block placement. In Proceedings of the International Symposium on Physical Design, pages 84-89, April 2004Google Scholar
  37. 37.
    A. Kennings and I.L. Markov. Analytical minimization of half-perimeter wirelength. In Proceedings of the Asia South Pacific Design Automation Conference, pages 179-184, Jan 2000Google Scholar
  38. 38.
    Andrew Kahng, Sherief Reda, and Qinke Wang. Architecture and details of a high quality, large-scale analytical placer. In Proceedings of the International Conference on Computer Aided Design, pages 891-899, Nov 2005Google Scholar
  39. 39.
    J.M. Kleinhans, G. Sigl, F.M. Johannes, and K.J. Antreich. Gordian: Vlsi placement by quadratic programming and slicing optimization. IEEE Trans. on Computer-Aided Design, CAD-10:356-365, 1991Google Scholar
  40. 40.
    A.B. Kahng and Q. Wang. Implementation and extensibility of an analytic placer. In Proceedings of the International Symposium on Physical Design, pages 18-25, 2004Google Scholar
  41. 41.
    Singh K, A. Wang, R. Brayton, and A. Sangiovanni-Vincentelli. Timing optimization of combinatorial logic. In Proceedings of the International Conference on Computer Aided Design, pages 282-285, Nov 1988Google Scholar
  42. 42.
    C.Li and C.-K. Koh. On improving recursive bipartitioning-based placement. Report tr-ece-03-14, Purdue University ECE, 2003Google Scholar
  43. 43.
    H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. Rectangle-packing-based module placement. In Proceedings of the International Conference on Computer Aided Design, pages 472-479, 1995Google Scholar
  44. 44.
    G.D. Micheli. Performance-oriented synthesis of large-scale domino cmos circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 6:751-765, 1987CrossRefGoogle Scholar
  45. 45.
    K.W. Morton and D.F. Mayers. Numerical Solution of Partial Differential Equations. Cambridge University Press, 1994Google Scholar
  46. 46.
    Gi-Joon Nam. Ispd 2006 placement contest: Benchmark suite and results. In Proceedings of the International Symposium on Physical Design, pages 167-167, 2006Google Scholar
  47. 47.
    Sudip Nag and Kamal Chaudhary. Post-placement residual-overlap removal with minimal movement. In Proceedings of the Design Automation and Test in Europe, pages 581-586, 1999Google Scholar
  48. 48.
    W. Naylor, R. Donelly, and L. Sha. Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer. US Patent 6301693, Oct 2001Google Scholar
  49. 49.
    A.N. Ng, I.L. Markov, R. Aggarwal, and V. Ramachandran. Solving hard instances of floorplacement. In Proceedings of the International Symposium on Physical Design, pages 170-177, New York, NY, USA, 2006. ACM PressGoogle Scholar
  50. 50.
    R. Okuda, T. Sato, H. Onodera, and K. Tamaru. An efficient algorithm for layout compaction problem with symmetry constraints. In Proceedings of the International Conference on Computer Aided Design, pages 148-153, November 1989Google Scholar
  51. 51.
    L.I. Rudin, S.J. Osher, and E. Fatermi. Nonlinear total variation based noise removal algorithms. Physica D, 60:259-268, 1992MATHCrossRefGoogle Scholar
  52. 52.
    J. Ruge and K. St üben. Algebraic multigrid. In S.F. McCormick, editor, Multigrid Methods, pages 73-80. SIAM, Philadelphia, 1987Google Scholar
  53. 53.
    H.V. Sorensen and C.S. Burrus. Fast dft and convolution algorithms. In S.K. Mitra and J.F. Kaiser, editors, Handbook for Digital Signal Processing. John Wiley and Sons, New York, 1993Google Scholar
  54. 54.
    K.J. Singh. Performance Optimization for Digital Circuits. PhD thesis, Computer Science Department, University of California Berkeley, 1992Google Scholar
  55. 55.
    U. Trottenberg, C.W. Oosterlee, and A. Sch üller. Multigrid. Academic Press, London, 2000Google Scholar
  56. 56.
    Xiaoping Tang, Ruiqi Tian, and Martin D.F. Wong. Optimal redistribution of white space for wire length minimization. In Proceedings of the Asia South Pacific Design Automation Conference, pages 412-417, January 2005Google Scholar
  57. 57.
    Taraneh Taghavi, Xiaojian Yang, and Bo-Kyung Choi. Dragon 2005: Large-scale mizedsize placement tool. In Proceedings of the International Symposium on Physical Design, April 2005Google Scholar
  58. 58.
    K.P. Vorwerk and A. Kennings. An improved mulit-level framework for force-directed placement. In Proceedings of the Design Automation and Test in Europe, volume 2, pages 240-245, 2005Google Scholar
  59. 59.
    K.P. Vorwerk, A. Kennings, and A. Vannelli. Engineering details of a stable forcedirected placer. In Proceedings of the International Conference on Computer Aided Design, pages 573-580, Nov 2004Google Scholar
  60. 60.
    Jens Vygen. Algorithms for large-scale flat placement. In Proceedings of the Design Automation Conference, pages 746-751, 1997Google Scholar
  61. 61.
    J. Vygen. Algorithms for detailed placement of standard cells. In Proceedings of the Design Automation and Test in Europe, pages 321-324, 1998Google Scholar
  62. 62.
    Songjie Xu. Synthesis for Hign-Density and High-Performance FPGA. PhD thesis, Computer Science Department, University of California, Los Angeles, 2000Google Scholar
  63. 63.
    Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, and Peter Suaris. Unified quadratic programming approach for mixed mode placement. In Proc. Int. Symposium on Physical Design, April 2005Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Tony F. Chan
    • 1
  • Kenton Sze
    • 1
  • Joseph R. Shinnerl
    • 2
  • Min Xie
    • 2
  1. 1.Los Angeles
  2. 2.Los Angeles

Personalised recommendations