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Simulation of Nano-CMOS Devices: From Atoms to Architecture

  • A. Asenov
  • A. R. Brown
  • B. Cheng
  • J. R. Watling
  • G. Roy
  • C. Alexander
Part of the Nanostructure Science and Technology book series (NST)

Abstract

The progressive scaling of transistors in complementary metal-oxide-semiconductor (CMOS) technology to achieve faster devices and higher device density and to reduce the cost per function has fueled the phenomenal growth and success of the semiconductor industry—captured over the past 40 years by Moore’s famous law. The International Technology Roadmap for Semiconductors (ITRS) predicts, as illustrated in Table 7.1, that 7-nm physical-gate-length CMOS transistors will be in mass production in 2018. The Roadmap of the leading integrated circuit (IC) manufacturer, IBM, goes further (see Table 7.2), predicting that the physical length of the transistors will reach 3 nm by 2025. Indeed, transistors with a 45-nm channel length are in mass production now in the 90-nm technology node and functioning transistors with a 4-nm channel length have been demonstrated already by NEC at IEDM 2003. Although it is clear that the scaling of the CMOS transistors will continue in the next two decades, it is widely recognized that intrinsic parameter fluctuations introduced by the discreteness of charge and matter will be a major factor limiting the integration of such devices with molecular dimensions in giga-transistor count chips.
TABLE 7.1.

Extract from theInternational Technology Roadmap forSemiconductors 2003.

TABLE 7.2.

IBMRoadmap, Dec. 2003.

Keywords

Monte Carlo Monte Carlo Simulation SRAM Cell CMOS Transistor Static Noise Margin 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • A. Asenov
    • 1
  • A. R. Brown
    • 1
  • B. Cheng
    • 1
  • J. R. Watling
    • 1
  • G. Roy
    • 1
  • C. Alexander
    • 1
  1. 1.Device Modelling Group, Dept. Electronics & Electrical EngineeringUniversity of GlasgowGlasgowScotland

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