Abstract
The progressive scaling of transistors in complementary metal-oxide-semiconductor (CMOS) technology to achieve faster devices and higher device density and to reduce the cost per function has fueled the phenomenal growth and success of the semiconductor industry—captured over the past 40 years by Moore’s famous law. The International Technology Roadmap for Semiconductors (ITRS) predicts, as illustrated in Table 7.1, that 7-nm physical-gate-length CMOS transistors will be in mass production in 2018. The Roadmap of the leading integrated circuit (IC) manufacturer, IBM, goes further (see Table 7.2), predicting that the physical length of the transistors will reach 3 nm by 2025. Indeed, transistors with a 45-nm channel length are in mass production now in the 90-nm technology node and functioning transistors with a 4-nm channel length have been demonstrated already by NEC at IEDM 2003. Although it is clear that the scaling of the CMOS transistors will continue in the next two decades, it is widely recognized that intrinsic parameter fluctuations introduced by the discreteness of charge and matter will be a major factor limiting the integration of such devices with molecular dimensions in giga-transistor count chips.
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References
A. Asenov, A.R. Brown, J.H. Davies and S. Saini, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 18, 1558 (1999).
D.J. Frank, Y. Taur, M. Ieong and H.-S.P. Wong, Symposium on VLSI Circuits Digest of Technical Papers, p. 171, (1999).
S. Kaya, A.R. Brown, A. Asenov, D. Magot and T. Linton, Proc. Simulation of Semiconductor Processes and Devices, (Athens, Greece, 2001), p. 78.
A. Asenov, Savas Kaya and Andrew R. Brown, IEEE Transactions on Electron Devices 50, 1254 (2003).
S.M. Goodnick, D.K. Ferry, C.W. Wilmsen, Z. Liliental, D. Fathy and O.L. Krivack, Phys. Rev. B. 32, 8171 (1985).
R.M. Feenstra, M.A. Lutz, F. Stern, K. Ismail, P. Mooney, F.K. LeGoues, C. Stanis, J.O. Chu and B.S. Meyerson, J. Vac. Sci. Technol. B. Microelectron. Process. Phenom. 13, 1608 (1995).
M. Niva, T. Kouzaki, K. Okada, M. Udagawa and R. Sinclair, Jpn. J. Appl. Phys. 33, 388 (1994).
D. Vasileska, W.J. Gross and D.K. Ferry, Extended Abstracts of the 6th International Workshop on Computational Electronics, IEEE Cat. No. 98EX116, (Osaka, Japan, 1998), p. 259.
A. Asenov, IEEE Trans. Electron Dev. 45, 2505 (1998).
H.K. Gummel, IEEE Trans. Electron Dev. 11, 455 (1964).
M.G. Ancona, Phys. Rev. B 42, 1222 (1990).
S. Jin, Y.J. Park and H.S. Min, Journal of Semiconductor Technology and Science 4, 32 (2004).
J.R. Watling, A.R. Brown, A. Asenov and D.K. Ferry, Proc. Simulation of Semiconductor Processes and Devices, (Athens, Greece, 2001), p. 82.
Z. Yu, R.W. Dutton, D.W. Yergeau and M.G. Ancona, Proc. Simulation of Semiconductor Processes and Devices, (Athens, Greece, 2001), p. 1.
J.R. Watling, A.R. Brown, A. Asenov, A. Svizhenko and M.P. Anantram, Proc. Simulation of Semiconductor Processes and Devices, (Kobe, Japan, 2002), p. 267.
G.D. Wilk, R.M. Wallace, J.M. Anthony, J. Appl. Phys. 89, 5243 (2001).
S. Jin, Y.J. Park and H.S. Min, Proc. Simulation of Semiconductor Processes and Devices, (Cambridge, MA, USA, 2003), p. 263.
A.T. Fromhold, Jr. Quantum Mechanics for Applied Physics and Engineering, (Dover Publications, Inc., New York, 1981).
A. Svizhenko, M.P. Anantram, T.R. Govindan, B. Biegel and R. Venugopal, J. Appl. Phys. 91, 2343 (2002).
T. Ezaki, T. Ikezawa, A. Notsu, K. Tanaka and M. Hane, Proc. Simulation of Semiconductor Processes and Devices, (Kobe, Japan, 2002), p. 91.
G. Roy, A.R. Brown, A. Asenov and S. Roy, J. Comp. Elec. 2, 323 (2003).
G. Roy, A.R. Brown, A. Asenov and S. Roy, Superlattices and Microstructures 34, 327 (2003).
A. Asenov, M. Jaraiz, S. Roy, G. Roy, F. Adamu-Lema, A.R. Brown, V. Moroz and R. Gafiteanu, Proc. Simulation of Semiconductor Processes and Devices, (Kobe, Japan, 2002), pp. 87.
N. Sano, K. Matsuzawa, M. Mukai and N Nakayama, International Electron Device Meeting (IEDM) Digest Tech. Papers, p. 275 (2000).
Z. Qin and S.T. Dunham, Proc. Mater. Res. Soc. Symp. 717, C3.8 (2002).
Z. Qin and S.T. Dunham, Phys. Rev B 68, 245201 (2003).
R.W. Hockney and J.W. Eastwood, Computer Simulation using Particles (McGraw-Hill, New York, 1981).
A. Asenov, R. Balasubramaniam, A.R. Brown and J.H. Davies, IEEE Trans. Electron Dev. 50, 839 (2003).
P.A. Stolk, F.P. Widdershoven and D.B. M Klaassen, IEEE Trans. Elec. Dev. 45, 1960 (1998).
T. Ezaki, T. Ikezawa and M. Hane, International Electron Device Meeting (IEDM) Digest Tech. Papers, p. 311, 2002.
C. Alexander, J.R. Watling, A.R. Brown and A. Asenov, Superlattices and Microstructures 34, 319 (2003).
W.J. Gross, D. Vasileska and D.K. Ferry, IEEE Trans. Elec. Dev. Lett. 20, 463 (1999).
C.J. Wordelman and U. Ravaioli, IEEE Trans. Elec. Dev. 47, 410 (2000).
S. Barraud, P. Dollfus, S. Galdin and P. Hesto, Solid State Electronics 46, 1061 (2002).
S.M. Ramey and D.K. Ferry, IEEE Trans. Nanotechnology 2, 193 (2003).
H.P. Tuinhout, Proc. 32th European Solid-State Device Research Conference (Florence, Italy, 2002) p. 95.
P.A. Stolk, H.P. Tuinhout, R. Duffy, E. Augendre, L.P. Bellefroid, M.J.B. Bolt, J. Croon, C.J.J. Dachs, F.R.J. Huisman, A.J. Moonen, Y.V. Ponomarev, R.F.M. Roes, M. Da Rold, E. Sevinck, K.N. Sreerambhatla, R. Surdeanu, R.M.D.A. Velghe, M. Vertregt, M.N. Webster, N.K.J. van Winkelhoff, A.G.A. Zegers-Van Duijnhoven, International Electron Device Meeting (IEDM) Digest Tech. Papers, p. 215 (2001).
K. Takeuchi, R. Koh, and T. Mogami, IEEE Trans. Elec. Dev. 48, 1995 (2001).
BSIM software, University of California, Berkeley, CA, USA, http://www-device.eecs.berkeley.edu/~bsim3/.
Aurora User’s Manual, Synopsys Inc., Mountain View, CA, USA, 2002.
E. Seevinck, F.J. List, and J. Lohstroh, IEEE J. Solid-State Circuits 22, 748 (1987).
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Asenov, A., Brown, A.R., Cheng, B., Watling, J.R., Roy, G., Alexander, C. (2007). Simulation of Nano-CMOS Devices: From Atoms to Architecture. In: Korkin, A., Gusev, E., Labanowski, J., Luryi, S. (eds) Nanotechnology for Electronic Materials and Devices. Nanostructure Science and Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-49965-9_7
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