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From SOI Basics to Nano-Size MOSFETs

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Book cover Nanotechnology for Electronic Materials and Devices

Part of the book series: Nanostructure Science and Technology ((NST))

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Abstract

Silicon-on-insulator (SOI) technology was initiated half a century ago for the fabrication of radiation-hard circuits. Several SOI materials and structures have been conceived for dielectrically separating the thin, active device volume from the silicon substrate (Fig. 2.1) [1], [2]. The background idea is that in a bulk silicon metal-oxide-semiconductor (MOS) transistor, only the superficial layer (0.1–0.2 µm thick) is actually useful for electron transport, whereas the substrate is causing undesirable effects to occur.

Basic architecture of fully depleted (a) and partially depleted CMOS transistors on SOI.

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Authors and Affiliations

  1. Institute of Microelectronics, Electromagnetism and Photonics (UMR CNRS-INPG-UJF), ENSERG, BP 257, 38016, Grenoble Cedex 1, France

    Sorin Cristoloveanu

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  1. Sorin Cristoloveanu
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Editors and Affiliations

  1. Nano & Giga Solutions, 1683 E. Spur Street, Gilbert, AZ, 85296, USA

    Anatoli Korkin

  2. IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY, 10598, USA

    Evgeni Gusev

  3. University of Notre Dame, 204A Nieuwland Science Hall, Notre Dame, IN, 46556, USA

    Jan Labanowski

  4. Department of Electrical and Computer Engineering, State University of New York at Stony Brook, Stony Brook, NY, 11794, USA

    Serge Luryi

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Cristoloveanu, S. (2007). From SOI Basics to Nano-Size MOSFETs. In: Korkin, A., Gusev, E., Labanowski, J., Luryi, S. (eds) Nanotechnology for Electronic Materials and Devices. Nanostructure Science and Technology. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-49965-9_2

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