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From SOI Basics to Nano-Size MOSFETs

  • Sorin Cristoloveanu
Part of the Nanostructure Science and Technology book series (NST)

Abstract

Silicon-on-insulator (SOI) technology was initiated half a century ago for the fabrication of radiation-hard circuits. Several SOI materials and structures have been conceived for dielectrically separating the thin, active device volume from the silicon substrate (Fig. 2.1) [1], [2]. The background idea is that in a bulk silicon metal-oxide-semiconductor (MOS) transistor, only the superficial layer (0.1–0.2 µm thick) is actually useful for electron transport, whereas the substrate is causing undesirable effects to occur.
FIGURE 2.1.

Basic architecture of fully depleted (a) and partially depleted CMOS transistors on SOI.

Keywords

Threshold Voltage Porous Silicon Charge Pump Subthreshold Swing Inversion Charge 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • Sorin Cristoloveanu
    • 1
  1. 1.Institute of Microelectronics, Electromagnetism and Photonics (UMR CNRS-INPG-UJF)ENSERGGrenoble Cedex 1France

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