The Common-Gate Configuration
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In the common gate configuration, the gate-to-source and the drain-to-source voltages, V GS and V DS , vary with the source-to-substrate voltage V S . As a result, the compact model parameters require continuing updating.
Figure 7.1 displays the drain current versus the source voltage V S of the 100 nm N-channel transistor considered in the previous chapter taking advantage of updated n, V To and I Suo parameters. The gate- and drain-to-substrate voltages are constant and respectively equal to 0.9 and 1.0 V. The currents predicted by the compact model with and without mobility degradation are represented respectively by the continuous and dashed curves. Crosses represent the ‘semi-empirical’ drain current. When V S is small, the impact of mobility degradation is considerable for the gate-to-source and drain-to-source voltages are large. As V S increases, the two curves concur progressively until they merge in weak inversion giving birth to the distinctive weak inversion straight line.