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The Real Intrinsic Gain Stage

  • Paul G. A. JespersEmail author
Chapter
  • 2.8k Downloads
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

In Chapter 1, the Intrinsic Gain Stage was sized in strong and weak inversion and, in Chapter 4, in moderate inversion. Only gradual channel models were utilized. The extension of the E.K.V model to short channel devices considered in Chapter 5 paves the way towards the sizing of real Intrinsic Gain Stages.

Keywords

Gate Voltage Drain Current Gate Length Drain Voltage Gate Width 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. Grabinski W, Nauwelaers B, Schreurs D (2006) Transistor level modelling for analog/RF IC design. Springer, The NetherlandsCrossRefGoogle Scholar
  2. Tsividis Y (1999) Operation and modelling of the MOS transistor, EE series. Mc-Graw Hill, New YorkGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Université Catholique de LouvainLouvain-la-NeuveBelgium

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