Abstract
In Chapter 1, the Intrinsic Gain Stage was sized in strong and weak inversion and, in Chapter 4, in moderate inversion. Only gradual channel models were utilized. The extension of the E.K.V model to short channel devices considered in Chapter 5 paves the way towards the sizing of real Intrinsic Gain Stages.
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Notes
- 1.
These consist of arrays controlled by the drain-to-source voltage V DS , the source-to-substrate voltage V S and the gate length L (see Annex 1).
- 2.
Computing the transfer function allows to evaluate harmonic distortion.
References
Grabinski W, Nauwelaers B, Schreurs D (2006) Transistor level modelling for analog/RF IC design. Springer, The Netherlands
Tsividis Y (1999) Operation and modelling of the MOS transistor, EE series. Mc-Graw Hill, New York
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Jespers, P.G.A. (2010). The Real Intrinsic Gain Stage. In: The g m /I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits. Analog Circuits and Signal Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-47101-3_6
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DOI: https://doi.org/10.1007/978-0-387-47101-3_6
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