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Sizing the Intrinsic Gain Stage

  • Paul G. A. JespersEmail author
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

Sizing methods assessing drain currents and gate widths of a simple circuit are reviewed in this chapter. The circuit, shown in Fig. 1.1, consists of a saturated common source transistor loaded by a capacitor. A constant current source is feeding the drain. The circuit is called currently the ‘Intrinsic Gain Stage’ (I.G.S.), the name ‘intrinsic’ underlining the fact that few parts aside the transistor control the performances of the circuit.

Our objective is to find gate widths and drain currents enabling to achieve a prescribed gain-bandwidth product ω T . We therefore consider the small signal equivalent circuitshown in Fig. 1.2. The input is an open circuit while the output consists of a dependent current source g m v in (where g m represents the transconductance of Q) in parallel with the output conductance g d and the capacitor C.

Keywords

Drain Current Bipolar Transistor Moderate Inversion Gate Length Gate Width 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. Binkley DM (2007) Tradeoffs and optimization in analog CMOS design. Wiley, Chichester, England, ISBN 978–0–470–03136–0Google Scholar
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  4. Silveira F, Flandre D, Jespers P (Sept 1996) A g m ∕ ​I D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silcon-on-isulator micropower OTA. IEEE J Solid State Circuits 31(9):1314–1319CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Université Catholique de LouvainLouvain-la-NeuveBelgium

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