Abstract
Sizing methods assessing drain currents and gate widths of a simple circuit are reviewed in this chapter. The circuit, shown in Fig. 1.1, consists of a saturated common source transistor loaded by a capacitor. A constant current source is feeding the drain. The circuit is called currently the ‘Intrinsic Gain Stage’ (I.G.S.), the name ‘intrinsic’ underlining the fact that few parts aside the transistor control the performances of the circuit.
Our objective is to find gate widths and drain currents enabling to achieve a prescribed gain-bandwidth product ω T . We therefore consider the small signal equivalent circuitshown in Fig. 1.2. The input is an open circuit while the output consists of a dependent current source g m v in (where g m represents the transconductance of Q) in parallel with the output conductance g d and the capacitor C.
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Notes
- 1.
Weak inversion occurs when MOS transistors are biased with gate voltages lower than the threshold voltage resulting in an exponential relationship between drain current and gate voltage (Vittoz 1977). Strong inversion designates the region where the classic quadratic current to voltage relationship holds true. The transition from weak to strong inversion is currently referred to as the moderate inversion region. This region plays a key role in CMOS analog circuits.
- 2.
- 3.
When I D and g m are interchanged, sizing is aiming at slew-rate instead of the gain-bandwidth product.
- 4.
BSIM is a widely used state-of-the-art model that is available in the public domain, see [BSIM]. It is based on threshold voltage formulations and this may explain some weaknesses in moderate inversion.
PSP for Penn State University and Philips (now NXP) is considered to be the more accurate industrial standard available nowadays (PSP 2006). It is based on the surface potential model (like the Charge Sheet Model).
- 5.
The method can be extended to other (trans)conductances. When the numerator and denominator of Eq. 1.17 are replaced respectively by g d and g d ∕ I D , the algorithm performs sizing in view of the output conductance.
References
Binkley DM (2007) Tradeoffs and optimization in analog CMOS design. Wiley, Chichester, England, ISBN 978–0–470–03136–0
Enz CC, Vittoz EA (2006) Charge-based MOS Transistor Modeling. The EKV model for low-power RF IC design. Wiley, Chichester
Girardi A, Cortes FP, Bampi S (2006) A tool for automatic design of analog circuits based on gm/ID methodology. IEEE ISCAS 2006
PSP (2006) http://pspmodel.asu.edu http://www.nxp.com/Philips_Models/mos_models/psp/
Silveira F, Flandre D, Jespers P (Sept 1996) A g m ∕ I D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silcon-on-isulator micropower OTA. IEEE J Solid State Circuits 31(9):1314–1319
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Jespers, P.G.A. (2010). Sizing the Intrinsic Gain Stage. In: The g m /I D Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits. Analog Circuits and Signal Processing. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-47101-3_1
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DOI: https://doi.org/10.1007/978-0-387-47101-3_1
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