Abstract
This chapter explores embedded microelectronic sub-systems by first defining the meaning of microelectronics packaging. Increasing the packaging density of electronic products, through techniques such as integral substrates and advanced interconnect, is a key issue. This challenge needs to be addressed inherently through electronic packaging in order to meet consumers demand for light-weight, compact, reliable and multifunctional electronic or communication devices. The technological advances, particularly 3-D packaging, which is driven by consumer demand can also enable concepts such as smart objects, smart spaces and augmented materials. This chapter provides a concise review of selected areas in 3-D packaging and then focuses upon two areas that may provide the type of flexibility and density required for future high-volume smart object development. These techniques are folded flex packaging and chip in laminate/interconnect.
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References
R. Tummala et al, “Microelectronics Packaging Handbook: Semiconductor Packaging”, Chapman & Hall, January 1997
S.L. Burkett et al, “Advanced Processing Techniques for Through-Wafer Interconnects,” Journal of Vacuum Science Technology B, Vol. 22, no. 1,pp 248–256, (Jan. 2004)
M. Sunohara et al, “Development of Wafer Thinning and Double Sided Bumping Technologies for Three Dimensional Stacked LSI”, In Proc. 52nd Electronic Components and Technology Conference, (May 28 31 May 2002), San Diego, California USA, pp. 238–245
R. Nagarajan, et al, “Development of a Novel Deep Silicon Tapered Via Etch Process for Through-Silicon Interconnection in 3D Integrated Systems”, In Proc. 56th Electronic Components and Technology Conference, (May 30 –June 2, 2006), San Diego, California, USA, pp 383–387
M. Bonkohara et al., “Trends and Opportunities of System-in-a-Package and Three-dimensional Integration”, Electronics and Communications in Japan (Part II: Electronics), Vol. 88, Issue 10, pp 37–49 (20 Sep 2005)
M. Kada, “The Dawn of 3D Packaging as System-in-Package (SIP)’” IEICE Transactions on Electronics, Special Issue on Integrated Systems with New Concepts, Vol. E84–C, No.12, Japan, ppl763–1770, (2003)
M. Karnezos et al, “System in a Package (SiP) Benefits and Technical Issues,” Proceedings of APEX, San Diego, (January 16–18, 2002), pp S15–1, 1 to 6
T. Kenji et al, “Current Status of Research and Development of Three Dimensional Chip Stack Technology”, Japanese Journal Of Applied Physics; Vol. 40, 2001, pp 3032–3037
ENIAC Strategic Research Agenda http://cordis.europa.eu/ist/eniac
C. Cahill et al, “Thermal Characterisation of Vertical Multichip Modules MCM-V”, IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol 18 No. 4, December 1995, pp 765–772
P. Ramm, et al, Japanese Journal of Applied Physics Vol. 43, No. 7A (2004), p. 829–830
K.N. Chen et al. “Morphology and bond strength of copper wafer bonding”, Electrochemical and Solid-State Letters 7, pp. G14–G16, 2004
R. R. Tummala et al, “Copper Interconnections for High Performance and Fine Pitch Flip-Chip Digital Applications and Ultraminiaturized RF Module Applications”, Proc 56th ECTC 2006 pp 102–111
N. Sillon et al, “Innovative Flip Chip Solution for System-On-Wafer Concept”, In Proc. First International Workshop on 3S (SOP, SIP, SOC) Electronic Technologies, (September 22–23, 2005), Atlanta, Georgia, USA
A. Mathewson et al, “Detailed Characterisation of Ni Microinsert Technology For Flip Chip Die on Wafer Attachment”, Proc 57th ECTC 2007 pp 616–621
Tessera’s Unique Approach to Stacked IC’s Packaging; Tessera Inc, http:// www.tessera.com/images/news_events/Stacked_packaging_backgrounder_05-25-01.pdf
Y J. Kim, “Folded Stack Package Development,” In Proc. 52nd Electronic Components and Technology Conference, (May 28 31 May 2002), San Diego, California USA, pp 1341–1346
B. Majeed et al, “Fabrication And Characterisation Of Flexible Substrates For Use In The Development Of Miniaturised Wireless Sensor Network Modules”, Journal of Electronic Packaging, Volume 128, Issue 3, pp. 236–245, September 2006
B. Majeed et al, “Microstructural, Mechanical, Fracturai and Electrical Characterisation of Thinned and Singulated Silicon Test Die”, J. Micromech. Microeng. Volume 16, Number 8, August 2006 pp. 1519–1529
I. Paul et al, “Statistical Fracture Modelling of Silicon with Varying Thickness”, Acta Materialia, Volume 54, Issue 15, Pages 3991–4000 (September 2006)
I. Paul et al, “Characterizing Stress in Ultra-Thin Silicon Wafers”, Applied Physics Letters 89, 073506 (2006)
E. M. Davis et al, “Solid logic technology: versatile high volume microelectronics”, IBM J. Res. Dev., vol. 8, pp.102, 1964.
L.F. Miller, “Controlled Collapse Reflow Chip Joining”, IBM Journal Research & Development, Vol. 13, pp 239–250, (1969)
S. Baba, “Low cost flip chip technology for organic substrates”, Fujitsu Sci. Tech. J. vol. 34, no.1, pp 78–86 September 1998.
R. Aschenbrenner et al, “Adhesive flip chip bonding of flexible substrates,” in Proc. 1st IEEE Int. Symp. Polym. Electron. Packag., 26–30 Oct 1997 pp: 86–94.
M. Abtewa et al, “Lead–free solders in microelectronics”, Mat. Sci. Eng., vol. 27, pp 95–141, 2000.
W. Kwang et al, “A new flip chip bonding technique using micromachined conductive polymer bumps”, IEEE Transactions on Advanced. Packaging, vol. 23, no 4, pp 586–591, November 1999.
R. W. Johnson et al, “Patterned adhesive flip chip technology for assembly on polyimide flex substrates”, Int. J. Microcirc. Electron. Packag., vol. 20, no. 3, pp 309–316, 3rd Qtr., 1997.
M. E. Wernle et al, “Advances in materials for low cost flip chip,” Adv. Microelec, pp 1–4, Summer 2000.
J. F. Zeberli et al, “Flip chip with studbumps and non conductive paste for CSP-3D”, in Proc. 13th Europ. Microelec. Packag. Conf, 2001, pp 314 319.
H. C. Cheng, et al, “Process-dependent contact characteristics of NCA assemblies,” IEEE Trans. Comp. Packag. Technol., vol. 27, no. 2, pp 398–410, June 2004.
B. Majeed et al,”Effect of Gold Stud Bump Topology on Reliability of Flip Chip on Flex Interconnects”, Accepted for IEEE Transactions on Advanced Packaging
S. C. O’Mathuna et al, “Test chips, Test Systems and thermal test data for multi-chip modules in the ESPRIT-APACHIP project”, IEEE Trans. Compon. Packag. Manuf. Technol. A Vol. 17, No. 3, pp 425 Sept. 1994
Texas Instruments (US Pat. No. 6,400,573 B1)
Electronic Package Technology Development Intel Packaging Journal, Volume 09, Issue 04, November 9, 2005
Ship Co. Patent WO2004/001848 A1 Electronics circuit manufacture
E. Jung et al, “Ultra Thin Chips for Miniaturised Products”, In Proc. 52nd Electronic Components and Technology Conference, (May 28 31 May 2002), San Diego, California USA, pp 1110–1113.
R. Aschenbrenner, et al, “Process flow and manufacturing concept for embedded active devices”, Proceedings of the Electronics Packaging Technology Conference EPTC, Dec 2004, pages 605–609.
B. C. Regan et al, “Nanocrystal-Powered Nanomotor”, Nano Lett.; 2005; 5(9); 1730–1733
K Jensen et al, “Nanotube Radio”, Nano Lett.; 2007; 7(11); 3508–3511
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Barton, J. (2008). Embedded Microelectronic Subsystems. In: Ambient Intelligence with Microsystems. Microsystems, vol 18. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-46264-6_6
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DOI: https://doi.org/10.1007/978-0-387-46264-6_6
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