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References
E. B. Eichelberger and T. W. Williams, “A logic design structure for LSI testability”, Journal of Design Automation and Fault Tolerant Computing, pp. 165-78, 1978.
[2] ANSI/IEEE Standard 1149. 1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standards Board, New York, N. Y, May 1990.
[3] P. Franco “Testing Digital Circuits for Timing Failures by Output Waveform Analysis”, Center for Reliable Computing Technical Report, No. 94-9 Stanford University, 1994.
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(2007). Testing. In: Physical Design Essentials. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-46115-1_6
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DOI: https://doi.org/10.1007/978-0-387-46115-1_6
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