Abstract
This paper considers the scheduling problem of core tests in a system. Our objective is to minimize the total system test time while respecting system constraints in terms of power consumption and test resource sharing. A simple and effective scheduling heuristic is proposed based on a no sessions based scheme for better overall test time optimisation.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35597-9_40
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© 2002 IFIP International Federation for Information Processing
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Flottes, ML., Pouget, J., Rouzeyre, B. (2002). Power-constrained Test Scheduling for SoCs under a “no session” scheme. In: Robert, M., Rouzeyre, B., Piguet, C., Flottes, ML. (eds) SOC Design Methodologies. IFIP — The International Federation for Information Processing, vol 90. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35597-9_34
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DOI: https://doi.org/10.1007/978-0-387-35597-9_34
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-6530-4
Online ISBN: 978-0-387-35597-9
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