Abstract
System chips are increasingly being designed by embedding reusable pre-designed and pre-verified cores. Modular, core-based test development is an attractive proposition for such large and complex ICs. This paper outlines the approach developed and used in Philips for core-based testing. It consists of four components: (1) a standardized set of test deliverables for a core, (2) standardized on-chip test access hardware, (3) a tool for translation of core tests into SOC tests, and (4) a tool for test scheduling.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35597-9_40
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© 2002 IFIP International Federation for Information Processing
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Marinissen, E.J. (2002). An Industrial Approach to Core-Based System Chip Testing. In: Robert, M., Rouzeyre, B., Piguet, C., Flottes, ML. (eds) SOC Design Methodologies. IFIP — The International Federation for Information Processing, vol 90. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35597-9_33
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DOI: https://doi.org/10.1007/978-0-387-35597-9_33
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-6530-4
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