Abstract
This paper describes the building of an original vision system on chip. Our smart sensor performs motion detection and pattern recognition with only one single line of pixels. The maximum cross-correlation number is processed by the processors network. A peculiar methodology was defined to tackle the sensor’s processing part design. Relying on our architectural synthesis tool GAUT, it leads to an optimal matching between the application specifications, the sensor’s architecture and the processor’s. The elementary processor’s architecture is detailed. Its CMOS VLSI implementation is sketched, as well as the sensor’s analog part and the light to byte conversion. The circuit’s final structure and floorplan are outlined. Its performances are exhibited.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35597-9_40
Chapter PDF
Similar content being viewed by others
Key words
References
Emzivat D., Gagnadre C. and Martin E. “Vision sensor for the industrial quality control”. Proceedings of the 7th International Conference on Image Processing and its Application, Manchester, UK, 12–15 July 1999.
Emzivat D., Gagnadre C. and Martin E. “Optical integrated circuit for the quality control ”. International Symposium on Microelectronic Manufacturing Technologies, Edimbourg, 19–21 May 1999.
Gruev V. and Etienne-Cummings R.R. “A programmable spatiotemporal image processor chip”. Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, May 28–31 2000.
Ishikawa M., Komuro, T., Ogawa K. and Ishii I. “A CMOS vision chip with SIMD processing element array for 1 ms image processing”. Abst. 1999 Dig. Tech. Papers of 1999 IEEE Int. Solid-State Circuits Conf.,pages 206–207.
Komuro T., Ishii I., Ishikawa M. and Yoshida A. “High speed target tracking vision chip”. Proceedings of the Fifth IEEE Int. Workshop on Computer Architecture for Machine Perception, Padova, Italy, September 11–13 2000, pages 49–56.
Martin E., Sentieys O., Dubois H. and Philippe J.L. “GAUT, An architectural synthesis tool for dedicated signal processors”. Proceedings of the EURO-DAC93, 1993.
Paillet F., Mercier D., Bernard T.M. and Senn E. “Low power issues in a digital programmable artificial retina”. IEEE Alessandro Volta Memorial International Workshop on Low Power Design, Como, Italy, March 4–5, 1999.
Paillet F. and Mercier, D. “Design solutions and techniques for vision system on a chip and fine-grain parallelism circuit integration”. Proceedings of the Thirteenth Annual IEEE International ASIC/SOC Conference, Arlington VA, USA, September 13–16 2000.
Senn E., Emzivat D. and Martin E. “A smart pixel sensor for industrial control”. International Symposium on Signals, Circuits and Systems, Iasi, Romania, July 10–11 2001.
Sicard G. “From biology to silicium: A bio-inspired analog retina for smart vision sensor”. PhD Thesis, Institut National Polytechnique de Grenoble, 1999.
Uyemura J.P. “Circuit design for CMOS VLSI”. Kluwer Academic Publishers, 1992.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 IFIP International Federation for Information Processing
About this chapter
Cite this chapter
Senn, E., Martin, E. (2002). A vision system on chip for industrial control. In: Robert, M., Rouzeyre, B., Piguet, C., Flottes, ML. (eds) SOC Design Methodologies. IFIP — The International Federation for Information Processing, vol 90. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35597-9_3
Download citation
DOI: https://doi.org/10.1007/978-0-387-35597-9_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-6530-4
Online ISBN: 978-0-387-35597-9
eBook Packages: Springer Book Archive