Abstract
A new efficient type I architecture for motion estimation in video sequences based on the Full-Search Block-Matching (FSBM) algorithm is proposed in this paper. This architecture presents minimum latency, maximum throughput and full utilization of the hardware resources, combining both pipelining and parallel processing techniques. The implementation of an array processor for motion estimation in a single-chip using 0.25 µm CMOS technology is presented. Experimental results show that this processor is able to estimate motion vectors in 4CIF video sequences at a rate of 16 frames/s.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35597-9_40
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© 2002 IFIP International Federation for Information Processing
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Roma, N., Sousa, L. (2002). A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation. In: Robert, M., Rouzeyre, B., Piguet, C., Flottes, ML. (eds) SOC Design Methodologies. IFIP — The International Federation for Information Processing, vol 90. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35597-9_22
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DOI: https://doi.org/10.1007/978-0-387-35597-9_22
Publisher Name: Springer, Boston, MA
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