Abstract
This paper presents the system architecture (with main details on each algorithm) of two ASIC for real time image processing designed with Aérospatiale-Matra industry. The first chip: OREC is dedicated to low level processing (edge detection) and includes a large 2D convolution filter 12×12, gradient computation, extraction of the local maxima of the gradient and thresholding. The second chip: OPNI is dedicated to intermediate level image processing. Processes or IP for edge thinning, region labeling, edge chaining (line segment extraction, line segment chaining, polygonal approximation and little chains elimination) are included in OPNI as well as a DSP core and a mathematical coprocessor based on Cordic method for trigonometric computations. Both VLSI chips have been successfully tested. They are used in a European project: obstacle detection for vehicule. The maximum frame rate reaches 25 images per second for 1024×1024 image size, and more than 110 images per second for 233×256 image size.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35597-9_40
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© 2002 IFIP International Federation for Information Processing
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Lamaty, P., Mazar, B., Demigny, D., Kessal, L., Karabernou, M. (2002). Two ASIC for Low and Middle Levels of Real Time Image Processing. In: Robert, M., Rouzeyre, B., Piguet, C., Flottes, ML. (eds) SOC Design Methodologies. IFIP — The International Federation for Information Processing, vol 90. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35597-9_1
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DOI: https://doi.org/10.1007/978-0-387-35597-9_1
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