Abstract
We pro vide a general definition of the 3-D wirelength placement problem. This definition facilitates comparison of 3-D placement algorithms. Wirelength results using partitioning placement are included for the A CM/SIGDA and ISPD98 standard benchmark circuit suites. Further, a wirelength comparison betw een 2- and 3-D placements is made, and it is shown that larger circuits require 50%–60% less wirelengthavhen utilising the third dimension.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35498-9_57
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© 2000 IFIP International Federation for Information Processing
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Obenaus, S.T., Szymanski, T.H. (2000). Placement Benchmarks for 3-D VLSI. In: Silveira, L.M., Devadas, S., Reis, R. (eds) VLSI: Systems on a Chip. IFIP — The International Federation for Information Processing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35498-9_40
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DOI: https://doi.org/10.1007/978-0-387-35498-9_40
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-1014-4
Online ISBN: 978-0-387-35498-9
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