Abstract
An operational amplifier designed with 0.35um CMOS technology is presented. All the transistors are realized with minimum or near-minimum channel length. As the short channel length causes performance degradation, a proper operational amplifier structure is selected to compensate the performance degradation. The op amp is designed to meet the requirement of high-speed high-resolution sigma delta modulators. It has a folded-cascode first stage and a class-A output stage. It features a DC gain of 78dB, an open-loop unity-gain frequency of 266MHZ, a slew rate of 650V/us, and consumes 10.2mW from a +/−1.5V power supply. High level simulation is used to evaluate the OTA performance in sigma delta modulators.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35498-9_57
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© 2000 IFIP International Federation for Information Processing
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Li, B., Tenhunen, H. (2000). A Design of Operational Amplifiers for Sigma Delta Modulators using 0.35um CMOS Process. In: Silveira, L.M., Devadas, S., Reis, R. (eds) VLSI: Systems on a Chip. IFIP — The International Federation for Information Processing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35498-9_3
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DOI: https://doi.org/10.1007/978-0-387-35498-9_3
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