Abstract
This article presents a self-timed approach to digital Gallium Arsenide logic applicable to high performance VLSI circuits and systems. The design techniques are based on GaAs Latch-Coupled FET Logic (LCFL) in order to achieve reasonable power-delay-area trade-off. The complexities due to clock skew are avoided and power savings achieved through the pipelined architecture. A range of arithmetic circuits is presented and their performance evaluated.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35498-9_57
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© 2000 IFIP International Federation for Information Processing
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Lachowicz, S., Eshraghian, K., Pfleiderer, HJ. (2000). Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI. In: Silveira, L.M., Devadas, S., Reis, R. (eds) VLSI: Systems on a Chip. IFIP — The International Federation for Information Processing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35498-9_22
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DOI: https://doi.org/10.1007/978-0-387-35498-9_22
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-1014-4
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