Abstract
In this paper1. we present a new architecture for low power floating point multiply — accumulate (MAC) fusion. The proposed architecture supports IEEE and non IEEE rounding modes. The functional partitioning of the adder segment of the MAC into three distinct, clock gated data paths allows activity reduction. The switching activity function of the adder is represented as a three state FSM. During any given operation cycle, only one of the data paths is active, during which occasion, the logic assertion status of the circuit nodes of the other data paths are maintained at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and data path simplifications. The proposed scheme offers a worst case power reduction of around 25%, in contrast to a comparable scheme reported in literature.
The original version of this chapter was revised: The copyright line was incorrect. This has been corrected. The Erratum to this chapter is available at DOI: 10.1007/978-0-387-35498-9_57
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© 2000 IFIP International Federation for Information Processing
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Pillai, R.V.K., Al-Khalili, D., Al-Khalili, A.J. (2000). An IEEE Compliant Floating Point MAF. In: Silveira, L.M., Devadas, S., Reis, R. (eds) VLSI: Systems on a Chip. IFIP — The International Federation for Information Processing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35498-9_14
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DOI: https://doi.org/10.1007/978-0-387-35498-9_14
Publisher Name: Springer, Boston, MA
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