Abstract
In this paper we describe Frontier, an FPGA placement system that uses design macro-blocks in conjuction with a series of placement algorithms to achieve highly-routable and high-performance layouts quickly. In the first stage of design placement, a macro-based floorplanner is used to quickly identify an initial layout based on inter-macro connectivity. Next, an FPGA routability metric, previously described in [10], is used to evaluate the quality of the initial placement. Finally, if the floorplan is determined to be unroutable, a feedback-driven placement perturbation step is employed to achieve a lower cost placement. For a collection of large reconfigurable computing benchmark circuits our placement system exhibits a 4 × speedup in combined place and route time versus commercial FPGA CAD software with improved design performance for most designs. It is shown that floorplanning, routability evaluation, and back-end optimization are all necessary to achieve efficient placement solutions.
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© 2000 IFIP International Federation for Information Processing
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Tessier, R. (2000). Frontier: A Fast Placement System for FPGAS. In: Silveira, L.M., Devadas, S., Reis, R. (eds) VLSI: Systems on a Chip. IFIP — The International Federation for Information Processing, vol 34. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35498-9_12
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DOI: https://doi.org/10.1007/978-0-387-35498-9_12
Publisher Name: Springer, Boston, MA
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